changeset 03efcdc3421f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=03efcdc3421f
description:
O3: Make O3 support variably lengthed instructions.
diffstat:
src/arch/alpha/predecoder.hh | 11 +-
src/arch/mips/predecoder.hh | 11 +-
src/arch/power/predecoder.hh | 8 +-
src/arch/sparc/predecoder.hh | 13 +-
src/cpu/base.hh | 3 +
src/cpu/o3/fetch.hh | 13 +-
src/cpu/o3/fetch_impl.hh | 272 +++++++++++++++++++++++-------------------
src/cpu/simple/base.hh | 3 -
8 files changed, 196 insertions(+), 138 deletions(-)
diffs (truncated from 689 to 300 lines):
diff -r ff2213d13e58 -r 03efcdc3421f src/arch/alpha/predecoder.hh
--- a/src/arch/alpha/predecoder.hh Mon Nov 15 14:04:05 2010 -0600
+++ b/src/arch/alpha/predecoder.hh Mon Nov 15 19:37:03 2010 -0800
@@ -47,10 +47,11 @@
// The extended machine instruction being generated
ExtMachInst ext_inst;
+ bool emiIsReady;
public:
Predecoder(ThreadContext * _tc)
- : tc(_tc)
+ : tc(_tc), emiIsReady(false)
{}
ThreadContext *
@@ -71,7 +72,9 @@
void
reset()
- { }
+ {
+ emiIsReady = false;
+ }
// Use this to give data to the predecoder. This should be used
// when there is control flow.
@@ -79,6 +82,7 @@
moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
{
ext_inst = inst;
+ emiIsReady = true;
#if FULL_SYSTEM
ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
#endif
@@ -93,13 +97,14 @@
bool
extMachInstReady()
{
- return true;
+ return emiIsReady;
}
// This returns a constant reference to the ExtMachInst to avoid a copy
const ExtMachInst &
getExtMachInst(PCState &pc)
{
+ emiIsReady = false;
return ext_inst;
}
};
diff -r ff2213d13e58 -r 03efcdc3421f src/arch/mips/predecoder.hh
--- a/src/arch/mips/predecoder.hh Mon Nov 15 14:04:05 2010 -0600
+++ b/src/arch/mips/predecoder.hh Mon Nov 15 19:37:03 2010 -0800
@@ -47,9 +47,10 @@
ThreadContext * tc;
//The extended machine instruction being generated
ExtMachInst emi;
+ bool emiIsReady;
public:
- Predecoder(ThreadContext * _tc) : tc(_tc)
+ Predecoder(ThreadContext * _tc) : tc(_tc), emiIsReady(false)
{}
ThreadContext *getTC()
@@ -70,7 +71,9 @@
void
reset()
- {}
+ {
+ emiIsReady = false;
+ }
//Use this to give data to the predecoder. This should be used
//when there is control flow.
@@ -78,6 +81,7 @@
moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
{
emi = inst;
+ emiIsReady = true;
}
bool
@@ -89,13 +93,14 @@
bool
extMachInstReady()
{
- return true;
+ return emiIsReady;
}
//This returns a constant reference to the ExtMachInst to avoid a copy
const ExtMachInst &
getExtMachInst(PCState &pc)
{
+ emiIsReady = false;
return emi;
}
};
diff -r ff2213d13e58 -r 03efcdc3421f src/arch/power/predecoder.hh
--- a/src/arch/power/predecoder.hh Mon Nov 15 14:04:05 2010 -0600
+++ b/src/arch/power/predecoder.hh Mon Nov 15 19:37:03 2010 -0800
@@ -51,10 +51,11 @@
// The extended machine instruction being generated
ExtMachInst emi;
+ bool emiIsReady;
public:
Predecoder(ThreadContext * _tc)
- : tc(_tc)
+ : tc(_tc), emiIsReady(false)
{
}
@@ -78,6 +79,7 @@
void
reset()
{
+ emiIsReady = false;
}
// Use this to give data to the predecoder. This should be used
@@ -86,6 +88,7 @@
moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
{
emi = inst;
+ emiIsReady = true;
}
// Use this to give data to the predecoder. This should be used
@@ -105,13 +108,14 @@
bool
extMachInstReady()
{
- return true;
+ return emiIsReady;
}
// This returns a constant reference to the ExtMachInst to avoid a copy
const ExtMachInst &
getExtMachInst(PCState &pcState)
{
+ emiIsReady = false;
return emi;
}
};
diff -r ff2213d13e58 -r 03efcdc3421f src/arch/sparc/predecoder.hh
--- a/src/arch/sparc/predecoder.hh Mon Nov 15 14:04:05 2010 -0600
+++ b/src/arch/sparc/predecoder.hh Mon Nov 15 19:37:03 2010 -0800
@@ -49,9 +49,10 @@
ThreadContext * tc;
// The extended machine instruction being generated
ExtMachInst emi;
+ bool emiIsReady;
public:
- Predecoder(ThreadContext * _tc) : tc(_tc)
+ Predecoder(ThreadContext * _tc) : tc(_tc), emiIsReady(false)
{}
ThreadContext *
@@ -67,7 +68,11 @@
}
void process() {}
- void reset() {}
+ void
+ reset()
+ {
+ emiIsReady = false;
+ }
// Use this to give data to the predecoder. This should be used
// when there is control flow.
@@ -87,6 +92,7 @@
emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
<< (sizeof(MachInst) * 8));
}
+ emiIsReady = true;
}
bool
@@ -98,13 +104,14 @@
bool
extMachInstReady()
{
- return true;
+ return emiIsReady;
}
// This returns a constant reference to the ExtMachInst to avoid a copy
const ExtMachInst &
getExtMachInst(PCState &pcState)
{
+ emiIsReady = false;
return emi;
}
};
diff -r ff2213d13e58 -r 03efcdc3421f src/cpu/base.hh
--- a/src/cpu/base.hh Mon Nov 15 14:04:05 2010 -0600
+++ b/src/cpu/base.hh Mon Nov 15 19:37:03 2010 -0800
@@ -180,6 +180,9 @@
public:
+ // Mask to align PCs to MachInst sized boundaries
+ static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
+
/// Provide access to the tracer pointer
Trace::InstTracer * getTracer() { return tracer; }
diff -r ff2213d13e58 -r 03efcdc3421f src/cpu/o3/fetch.hh
--- a/src/cpu/o3/fetch.hh Mon Nov 15 14:04:05 2010 -0600
+++ b/src/cpu/o3/fetch.hh Mon Nov 15 19:37:03 2010 -0800
@@ -235,13 +235,14 @@
* Fetches the cache line that contains fetch_PC. Returns any
* fault that happened. Puts the data into the class variable
* cacheData.
- * @param fetch_PC The PC address that is being fetched from.
+ * @param vaddr The memory address that is being fetched from.
* @param ret_fault The fault reference that will be set to the result of
* the icache access.
* @param tid Thread id.
+ * @param pc The actual PC of the current instruction.
* @return Any fault that occured.
*/
- bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid);
+ bool fetchCacheLine(Addr vaddr, Fault &ret_fault, ThreadID tid, Addr pc);
/** Squashes a specific thread and resets the PC. */
inline void doSquash(const TheISA::PCState &newPC, ThreadID tid);
@@ -291,6 +292,10 @@
}
private:
+ DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
+ StaticInstPtr curMacroop, TheISA::PCState thisPC,
+ TheISA::PCState nextPC, bool trace);
+
/** Handles retrying the fetch access. */
void recvRetry();
@@ -347,6 +352,10 @@
TheISA::PCState pc[Impl::MaxThreads];
+ Addr fetchOffset[Impl::MaxThreads];
+
+ StaticInstPtr macroop[Impl::MaxThreads];
+
/** Memory request used to access cache. */
RequestPtr memReq[Impl::MaxThreads];
diff -r ff2213d13e58 -r 03efcdc3421f src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Mon Nov 15 14:04:05 2010 -0600
+++ b/src/cpu/o3/fetch_impl.hh Mon Nov 15 19:37:03 2010 -0800
@@ -317,6 +317,8 @@
// Setup PC and nextPC with initial state.
for (ThreadID tid = 0; tid < numThreads; tid++) {
pc[tid] = cpu->pcState(tid);
+ fetchOffset[tid] = 0;
+ macroop[tid] = NULL;
}
for (ThreadID tid = 0; tid < numThreads; tid++) {
@@ -534,7 +536,8 @@
template <class Impl>
bool
-DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID
tid)
+DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, Fault &ret_fault, ThreadID tid,
+ Addr pc)
{
Fault fault = NoFault;
@@ -547,7 +550,7 @@
DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
tid);
return false;
- } else if (interruptPending && !(fetch_PC & 0x3)) {
+ } else if (interruptPending && !(pc & 0x3)) {
// Hold off fetch from getting new instructions when:
// Cache is blocked, or
// while an interrupt is pending and we're not in PAL mode, or
@@ -557,8 +560,8 @@
return false;
}
- // Align the fetch PC so it's at the start of a cache block.
- Addr block_PC = icacheBlockAlignPC(fetch_PC);
+ // Align the fetch address so it's at the start of a cache block.
+ Addr block_PC = icacheBlockAlignPC(vaddr);
// If we've already got the block, no need to try to fetch it again.
if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) {
@@ -570,7 +573,7 @@
// Build request here.
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