My initial reaction is "even if this works, this can't possibly be the best way to do it"... where do APIC messages live in the address space? How does 'Addr.max >> 4' let them through? Did you really think this change didn't need a comment? ;-)
On Tue, Nov 23, 2010 at 3:39 AM, Gabe Black <gbl...@eecs.umich.edu> wrote: > This seems to get APIC messages back to the CPU, but I really don't know > if it's the right way to do this. I have the feeling there are forces at > work in this code I don't fully appreciate. > > Gabe > > Gabe Black wrote: > > This is an automatically generated e-mail. To reply, visit: > > http://reviews.m5sim.org/r/323/ > > > > > > Review request for Default. > > By Gabe Black. > > > > > > Description > > > > Mem,X86: Make the IO bridge pass APIC messages back towards the CPU. > > > > > > Diffs > > > > * configs/example/fs.py (865e37d507c7) > > > > View Diff <http://reviews.m5sim.org/r/323/diff/> > > > > ------------------------------------------------------------------------ > > > > _______________________________________________ > > m5-dev mailing list > > m5-dev@m5sim.org > > http://m5sim.org/mailman/listinfo/m5-dev > > > > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev >
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