On Wed, Dec 1, 2010 at 3:07 PM, Ali Saidi <sa...@umich.edu> wrote: > Continuing the e-mail thread that never dies.... > > It appears as though the dcache some how does the correct thing when a read > request comes into the l2 bus. Note that the dcache is snooping the > request. > Listening for system connection on port 3456 > > 481100500: system.cpu.dtb.walker: Begining table walk for address > 0xc0200000, TTBCR: 0, bits:0 > 481100500: system.cpu.dtb.walker: - Selecting TTBR0 > 481100500: system.cpu.dtb.walker: - Descriptor at address 0x7008 > 481100500: system.tol2bus: recvAtomic: packet src 4 dest -1 addr 0x7008 cmd > ReadReq > 481100500: system.cpu.dcache: snooped a ReadReq request for addr 7000, > responding, new state is 13 > 481100500: system.l2: rcvd mem-inhibited ReadReq on 0x7008: not responding > 481100500: system.cpu.dtb.walker: L1 descriptor for 0xc0200000 is 0x20040e > > After some work I managed to get a cache to work in this case too.... The > table walker has to kick off a sendStatusChange() otherwise the cache below > it doesn't get added to the snooping list of the tol2bus. >
I'm not too surprised that reads work, but what about writes (e.g., if the TLB walker sets an accessed bit)? Steve
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