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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA. Diffs ----- src/arch/arm/predecoder.hh 2b5fbdcbfb5d src/arch/arm/predecoder.cc 2b5fbdcbfb5d src/cpu/o3/fetch_impl.hh 2b5fbdcbfb5d Diff: http://reviews.m5sim.org/r/341/diff Testing ------- Thanks, Ali
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