changeset bafa8a197088 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bafa8a197088
description:
O3: Allow a store entry to store up to 16 bytes (instead of
TheISA::IntReg).
The store queue doesn't need to be ISA specific and architectures can
frequently store more than an int registers worth of data. A 128 bits
seems
more common, but even 256 bits may be appropriate. Pretty much anything
less
than a cache line size is buildable.
diffstat:
src/cpu/o3/lsq_unit.hh | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diffs (21 lines):
diff -r 7506ba7f2cdb -r bafa8a197088 src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh Tue Dec 07 16:19:57 2010 -0800
+++ b/src/cpu/o3/lsq_unit.hh Tue Dec 07 16:19:57 2010 -0800
@@ -63,8 +63,6 @@
*/
template <class Impl>
class LSQUnit {
- protected:
- typedef TheISA::IntReg IntReg;
public:
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr;
@@ -338,7 +336,7 @@
/** The size of the store. */
int size;
/** The store data. */
- char data[sizeof(IntReg)];
+ char data[16];
/** Whether or not the store is split into two requests. */
bool isSplit;
/** Whether or not the store can writeback. */
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