changeset f455790bcd47 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f455790bcd47
description:
X86: Take advantage of new PCState syntax.
diffstat:
src/arch/x86/isa/decoder/two_byte_opcodes.isa | 4 ++--
src/arch/x86/isa/microops/regop.isa | 13 +++----------
src/arch/x86/isa/microops/seqop.isa | 16 ++++------------
src/arch/x86/isa/operands.isa | 6 +++++-
4 files changed, 14 insertions(+), 25 deletions(-)
diffs (91 lines):
diff -r 4dd870e2c91d -r f455790bcd47
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Tue Dec 07 23:08:05
2010 -0800
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Wed Dec 08 00:27:23
2010 -0800
@@ -198,8 +198,8 @@
}}, IsNonSpeculative);
#endif
0x54: m5panic({{
- panic("M5 panic instruction called at pc=%#x.\n",
- xc->pcState().pc());
+ panic("M5 panic instruction called at pc = %#x.\n",
+ RIP);
}}, IsNonSpeculative);
0x55: m5reserved1({{
warn("M5 reserved opcode 1 ignored.\n");
diff -r 4dd870e2c91d -r f455790bcd47 src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Tue Dec 07 23:08:05 2010 -0800
+++ b/src/arch/x86/isa/microops/regop.isa Wed Dec 08 00:27:23 2010 -0800
@@ -944,12 +944,8 @@
code = 'DoubleBits = psrc1 ^ op2;'
class Wrip(WrRegOp, CondRegOp):
- code = '''
- X86ISA::PCState pc = PCS;
- pc.npc(psrc1 + sop2 + CSBase);
- PCS = pc;
- '''
- else_code = "PCS = PCS;"
+ code = 'NRIP = psrc1 + sop2 + CSBase;'
+ else_code = "NRIP = NRIP;"
class Wruflags(WrRegOp):
code = 'ccFlagBits = psrc1 ^ op2'
@@ -965,10 +961,7 @@
'''
class Rdip(RdRegOp):
- code = '''
- X86ISA::PCState pc = PCS;
- DestReg = pc.npc() - CSBase;
- '''
+ code = 'DestReg = NRIP - CSBase;'
class Ruflags(RdRegOp):
code = 'DestReg = ccFlagBits'
diff -r 4dd870e2c91d -r f455790bcd47 src/arch/x86/isa/microops/seqop.isa
--- a/src/arch/x86/isa/microops/seqop.isa Tue Dec 07 23:08:05 2010 -0800
+++ b/src/arch/x86/isa/microops/seqop.isa Wed Dec 08 00:27:23 2010 -0800
@@ -169,23 +169,15 @@
return super(Eret, self).getAllocator(microFlags)
iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
- {"code": '''
- X86ISA::PCState pc = PCS;
- pc.nupc(target);
- PCS = pc;
- ''',
- "else_code": "PCS = PCS",
+ {"code": "nuIP = target;",
+ "else_code": "nuIP = nuIP;",
"cond_test": "checkCondition(ccFlagBits, cc)"})
exec_output += SeqOpExecute.subst(iop)
header_output += SeqOpDeclare.subst(iop)
decoder_output += SeqOpConstructor.subst(iop)
iop = InstObjParams("br", "MicroBranch", "SeqOpBase",
- {"code": '''
- X86ISA::PCState pc = PCS;
- pc.nupc(target);
- PCS = pc;
- ''',
- "else_code": "PCS = PCS",
+ {"code": "nuIP = target;",
+ "else_code": "nuIP = nuIP;",
"cond_test": "true"})
exec_output += SeqOpExecute.subst(iop)
header_output += SeqOpDeclare.subst(iop)
diff -r 4dd870e2c91d -r f455790bcd47 src/arch/x86/isa/operands.isa
--- a/src/arch/x86/isa/operands.isa Tue Dec 07 23:08:05 2010 -0800
+++ b/src/arch/x86/isa/operands.isa Wed Dec 08 00:27:23 2010 -0800
@@ -97,7 +97,11 @@
'FpSrcReg2': floatReg('src2', 21),
'FpDestReg': floatReg('dest', 22),
'FpData': floatReg('data', 23),
- 'PCS': ('PCState', 'udw', None,
+ 'RIP': ('PCState', 'uqw', 'pc',
+ (None, None, 'IsControl'), 50),
+ 'NRIP': ('PCState', 'uqw', 'npc',
+ (None, None, 'IsControl'), 50),
+ 'nuIP': ('PCState', 'uqw', 'nupc',
(None, None, 'IsControl'), 50),
# This holds the condition code portion of the flag register. The
# nccFlagBits version holds the rest.
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