changeset 8a7ba5a1b35d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8a7ba5a1b35d
description:
Alpha: Take advantage of new PCState syntax.
diffstat:
src/arch/alpha/isa/branch.isa | 19 +++++++++----------
src/arch/alpha/isa/decoder.isa | 13 +++++--------
src/arch/alpha/isa/main.isa | 3 ++-
3 files changed, 16 insertions(+), 19 deletions(-)
diffs (103 lines):
diff -r 8ac74e34c6f4 -r 8a7ba5a1b35d src/arch/alpha/isa/branch.isa
--- a/src/arch/alpha/isa/branch.isa Wed Dec 08 10:45:14 2010 -0800
+++ b/src/arch/alpha/isa/branch.isa Wed Dec 08 10:55:33 2010 -0800
@@ -221,10 +221,10 @@
code = '''
bool cond;
%(code)s;
- PCState pc = PCS;
if (cond)
- pc.npc(pc.npc() + disp);
- PCS = pc;
+ NPC = NPC + disp;
+ else
+ NPC = NPC;
''' % { "code" : code }
iop = InstObjParams(name, Name, 'Branch', code,
('IsDirectControl', 'IsCondControl'))
@@ -237,18 +237,17 @@
let {{
def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
# Declare basic control transfer w/o link (i.e. link reg is R31)
- readpc_code = 'PCState pc = PCS;'
- nolink_code = 'pc.npc(%s);\nPCS = pc' % npc_expr
+ nolink_code = 'NPC = %s;\n' % npc_expr
nolink_iop = InstObjParams(name, Name, base_class,
- readpc_code + nolink_code, flags)
+ nolink_code, flags)
header_output = BasicDeclare.subst(nolink_iop)
decoder_output = BasicConstructor.subst(nolink_iop)
exec_output = BasicExecute.subst(nolink_iop)
# Generate declaration of '*AndLink' version, append to decls
- link_code = 'Ra = pc.npc() & ~3;\n' + nolink_code
+ link_code = 'Ra = NPC & ~3;\n' + nolink_code
link_iop = InstObjParams(name, Name + 'AndLink', base_class,
- readpc_code + link_code, flags)
+ link_code, flags)
header_output += BasicDeclare.subst(link_iop)
decoder_output += BasicConstructor.subst(link_iop)
exec_output += BasicExecute.subst(link_iop)
@@ -263,13 +262,13 @@
def format UncondBranch(*flags) {{
flags += ('IsUncondControl', 'IsDirectControl')
(header_output, decoder_output, decode_block, exec_output) = \
- UncondCtrlBase(name, Name, 'Branch', 'pc.npc() + disp', flags)
+ UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
}};
def format Jump(*flags) {{
flags += ('IsUncondControl', 'IsIndirectControl')
(header_output, decoder_output, decode_block, exec_output) = \
- UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (pc.npc() & 1)', flags)
+ UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
}};
diff -r 8ac74e34c6f4 -r 8a7ba5a1b35d src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa Wed Dec 08 10:45:14 2010 -0800
+++ b/src/arch/alpha/isa/decoder.isa Wed Dec 08 10:55:33 2010 -0800
@@ -850,10 +850,8 @@
bool dopal = xc->simPalCheck(palFunc);
if (dopal) {
- PCState pc = PCS;
- xc->setMiscReg(IPR_EXC_ADDR, pc.npc());
- pc.npc(xc->readMiscReg(IPR_PAL_BASE) + palOffset);
- PCS = pc;
+ xc->setMiscReg(IPR_EXC_ADDR, NPC);
+ NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
}
}
}}, IsNonSpeculative);
@@ -1019,14 +1017,13 @@
}}, IsNonSpeculative);
#endif
0x54: m5panic({{
- panic("M5 panic instruction called at pc=%#x.",
- xc->pcState().pc());
+ panic("M5 panic instruction called at pc = %#x.", PC);
}}, IsNonSpeculative);
#define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase())
0x55: decode RA {
0x00: m5a_old({{
- panic("Deprecated M5 annotate instruction executed at
pc=%#x\n",
- xc->pcState().pc());
+ panic("Deprecated M5 annotate instruction executed "
+ "at pc = %#x\n", PC);
}}, IsNonSpeculative);
0x01: m5a_bsm({{
CPANN(swSmBegin);
diff -r 8ac74e34c6f4 -r 8a7ba5a1b35d src/arch/alpha/isa/main.isa
--- a/src/arch/alpha/isa/main.isa Wed Dec 08 10:45:14 2010 -0800
+++ b/src/arch/alpha/isa/main.isa Wed Dec 08 10:55:33 2010 -0800
@@ -186,7 +186,8 @@
'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
- 'PCS': ('PCState', 'uq', None, ( None, None, 'IsControl' ), 4),
+ 'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4),
+ 'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4),
'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
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