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Seems basically ok to me. It's a little odd to have mispredicts on non-control instructions, but that's how ARM does things I guess. Perhaps you could make the ISA description mark instructions changing R15 as control instructions? I'm sure that would be harder than it sounds. src/cpu/o3/fetch_impl.hh <http://reviews.m5sim.org/r/343/#comment776> I don't think there's actually a rule about it, but this || at the start of the line looks a little funny. I like them at the end of the line since that visually indicates the expression continues. Not a big deal, but it would be nice to move it. src/cpu/o3/fetch_impl.hh <http://reviews.m5sim.org/r/343/#comment777> I was really confused here for a second until I realized review board was ignoring the change in indentation. - Gabe On 2010-12-06 16:12:44, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/343/ > ----------------------------------------------------------- > > (Updated 2010-12-06 16:12:44) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > Fix mispredicts from non control instructions. The squash inside the > fetch unit should not attempt to remove them from the branch predictor > as non-control instructions are not pushed into the predictor. > > > Diffs > ----- > > src/cpu/o3/comm.hh 2b5fbdcbfb5d > src/cpu/o3/commit_impl.hh 2b5fbdcbfb5d > src/cpu/o3/fetch_impl.hh 2b5fbdcbfb5d > src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d > > Diff: http://reviews.m5sim.org/r/343/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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