changeset 998b217dcae7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=998b217dcae7
description:
ARM: Take advantage of new PCState syntax.
diffstat:
src/arch/arm/isa/insts/branch.isa | 55 ++----
src/arch/arm/isa/insts/data.isa | 9 +-
src/arch/arm/isa/insts/ldr.isa | 9 +-
src/arch/arm/isa/insts/macromem.isa | 4 +-
src/arch/arm/isa/insts/misc.isa | 29 +--
src/arch/arm/isa/operands.isa | 281 ++++++++++++++++++++---------------
6 files changed, 198 insertions(+), 189 deletions(-)
diffs (truncated from 558 to 300 lines):
diff -r 9bd6b37d0189 -r 998b217dcae7 src/arch/arm/isa/insts/branch.isa
--- a/src/arch/arm/isa/insts/branch.isa Thu Dec 09 14:45:04 2010 -0800
+++ b/src/arch/arm/isa/insts/branch.isa Thu Dec 09 14:45:17 2010 -0800
@@ -46,17 +46,14 @@
# B, BL
for (mnem, link) in (("b", False), ("bl", True)):
bCode = '''
- ArmISA::PCState pc = PCS;
- Addr curPc = pc.instPC();
- pc.instNPC((uint32_t)(curPc + imm));
- PCS = pc;
+ NPC = (uint32_t)(PC + imm);
'''
if (link):
bCode += '''
- if (pc.thumb())
- LR = curPc | 1;
+ if (Thumb)
+ LR = PC | 1;
else
- LR = curPc - 4;
+ LR = PC - 4;
'''
bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
@@ -68,12 +65,9 @@
# BX, BLX
blxCode = '''
- ArmISA::PCState pc = PCS;
- Addr curPc M5_VAR_USED = pc.instPC();
%(link)s
// Switch modes
%(branch)s
- PCS = pc;
'''
blxList = (("blx", True, True),
@@ -85,8 +79,8 @@
if imm:
Name += "Imm"
# Since we're switching ISAs, the target ISA will be the opposite
- # of the current ISA. pc.thumb() is whether the target is ARM.
- newPC = '(pc.thumb() ? (roundDown(curPc, 4) + imm) : (curPc +
imm))'
+ # of the current ISA. Thumb is whether the target is ARM.
+ newPC = '(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))'
base = "BranchImmCond"
declare = BranchImmCondDeclare
constructor = BranchImmCondConstructor
@@ -101,28 +95,28 @@
// The immediate version of the blx thumb instruction
// is 32 bits wide, but "next pc" doesn't reflect that
// so we don't want to substract 2 from it at this point
- if (pc.thumb())
- LR = curPc | 1;
+ if (Thumb)
+ LR = PC | 1;
else
- LR = curPc - 4;
+ LR = PC - 4;
'''
elif link:
linkStr = '''
- if (pc.thumb())
- LR = (curPc - 2) | 1;
+ if (Thumb)
+ LR = (PC - 2) | 1;
else
- LR = curPc - 4;
+ LR = PC - 4;
'''
else:
linkStr = ""
if imm and link: #blx with imm
branchStr = '''
- pc.nextThumb(!pc.thumb());
- pc.instNPC(%(newPC)s);
+ NextThumb = !Thumb;
+ NPC = %(newPC)s;
'''
else:
- branchStr = "pc.instIWNPC(%(newPC)s);"
+ branchStr = "IWNPC = %(newPC)s;"
branchStr = branchStr % { "newPC" : newPC }
code = blxCode % {"link": linkStr,
@@ -139,12 +133,7 @@
#CBNZ, CBZ. These are always unconditional as far as predicates
for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")):
- code = '''
- ArmISA::PCState pc = PCS;
- Addr curPc = pc.instPC();
- pc.instNPC((uint32_t)(curPc + imm));
- PCS = pc;
- '''
+ code = 'NPC = (uint32_t)(PC + imm);\n'
predTest = "Op1 %(test)s 0" % {"test": test}
iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
{"code": code, "predicate_test": predTest})
@@ -161,11 +150,7 @@
ArmISA::TLB::MustBeOne;
EA = Op1 + Op2 * 2
'''
- accCode = '''
- ArmISA::PCState pc = PCS;
- pc.instNPC(pc.instPC() + 2 * (Mem.uh));
- PCS = pc;
- '''
+ accCode = 'NPC = PC + 2 * (Mem.uh);\n'
mnem = "tbh"
else:
eaCode = '''
@@ -174,11 +159,7 @@
ArmISA::TLB::MustBeOne;
EA = Op1 + Op2
'''
- accCode = '''
- ArmISA::PCState pc = PCS;
- pc.instNPC(pc.instPC() + 2 * (Mem.ub));
- PCS = pc;
- '''
+ accCode = 'NPC = PC + 2 * (Mem.ub)'
mnem = "tbb"
iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
{'ea_code': eaCode,
diff -r 9bd6b37d0189 -r 998b217dcae7 src/arch/arm/isa/insts/data.isa
--- a/src/arch/arm/isa/insts/data.isa Thu Dec 09 14:45:04 2010 -0800
+++ b/src/arch/arm/isa/insts/data.isa Thu Dec 09 14:45:17 2010 -0800
@@ -239,10 +239,8 @@
cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true,
sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
CondCodes = CondCodesMask & newCpsr;
- ArmISA::PCState pc = PCS;
- pc.nextThumb(((CPSR)newCpsr).t);
- pc.nextJazelle(((CPSR)newCpsr).j);
- PCS = pc;
+ NextThumb = ((CPSR)newCpsr).t;
+ NextJazelle = ((CPSR)newCpsr).j;
'''
buildImmDataInst(mnem + 's', code, flagType,
suffix = "ImmPclr", buildCc = False,
@@ -257,8 +255,7 @@
buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
buildImmDataInst("adr", '''
- ArmISA::PCState pc = PCS;
- Dest = resTemp = (pc.instPC() & ~0x3) +
+ Dest = resTemp = (PC & ~0x3) +
(op1 ? secondOp : -secondOp);
''')
buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
diff -r 9bd6b37d0189 -r 998b217dcae7 src/arch/arm/isa/insts/ldr.isa
--- a/src/arch/arm/isa/insts/ldr.isa Thu Dec 09 14:45:04 2010 -0800
+++ b/src/arch/arm/isa/insts/ldr.isa Thu Dec 09 14:45:17 2010 -0800
@@ -105,16 +105,15 @@
accCode = '''
CPSR cpsr = Cpsr;
SCTLR sctlr = Sctlr;
- ArmISA::PCState pc = PCS;
- pc.instNPC(cSwap<uint32_t>(Mem.ud, cpsr.e));
+ // Use the version of NPC that gets set before NextThumb
+ pNPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
uint32_t newCpsr =
cpsrWriteByInstr(cpsr | CondCodes,
cSwap<uint32_t>(Mem.ud >> 32, cpsr.e),
0xF, true, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
- pc.nextThumb(((CPSR)newCpsr).t);
- pc.nextJazelle(((CPSR)newCpsr).j);
- PCS = pc;
+ NextThumb = ((CPSR)newCpsr).t;
+ NextJazelle = ((CPSR)newCpsr).j;
CondCodes = CondCodesMask & newCpsr;
'''
self.codeBlobs["memacc_code"] = accCode
diff -r 9bd6b37d0189 -r 998b217dcae7 src/arch/arm/isa/insts/macromem.isa
--- a/src/arch/arm/isa/insts/macromem.isa Thu Dec 09 14:45:04 2010 -0800
+++ b/src/arch/arm/isa/insts/macromem.isa Thu Dec 09 14:45:17 2010 -0800
@@ -93,9 +93,7 @@
cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
CondCodes = CondCodesMask & newCpsr;
- ArmISA::PCState pc = PCS;
- pc.instIWNPC(cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0));
- PCS = pc;
+ IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
'''
microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
'MicroMemOp',
diff -r 9bd6b37d0189 -r 998b217dcae7 src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa Thu Dec 09 14:45:04 2010 -0800
+++ b/src/arch/arm/isa/insts/misc.isa Thu Dec 09 14:45:17 2010 -0800
@@ -83,10 +83,8 @@
uint32_t newCpsr =
cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false,
sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
- ArmISA::PCState pc = PCS;
- pc.nextThumb(((CPSR)newCpsr).t);
- pc.nextJazelle(((CPSR)newCpsr).j);
- PCS = pc;
+ NextThumb = ((CPSR)newCpsr).t;
+ NextJazelle = ((CPSR)newCpsr).j;
CondCodes = CondCodesMask & newCpsr;
'''
msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
@@ -111,10 +109,8 @@
uint32_t newCpsr =
cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false,
sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
- ArmISA::PCState pc = PCS;
- pc.nextThumb(((CPSR)newCpsr).t);
- pc.nextJazelle(((CPSR)newCpsr).j);
- PCS = pc;
+ NextThumb = ((CPSR)newCpsr).t;
+ NextJazelle = ((CPSR)newCpsr).j;
CondCodes = CondCodesMask & newCpsr;
'''
msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
@@ -470,10 +466,7 @@
decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
exec_output += PredOpExecute.subst(usada8Iop)
- bkptCode = '''
- ArmISA::PCState pc = PCS;
- return new PrefetchAbort(pc.pc(), ArmFault::DebugEvent);
- '''
+ bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
bkptCode)
header_output += BasicDeclare.subst(bkptIop)
@@ -650,10 +643,8 @@
exec_output += PredOpExecute.subst(mcr15UserIop)
enterxCode = '''
- ArmISA::PCState pc = PCS;
- pc.nextThumb(true);
- pc.nextJazelle(true);
- PCS = pc;
+ NextThumb = true;
+ NextJazelle = true;
'''
enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
{ "code": enterxCode,
@@ -663,10 +654,8 @@
exec_output += PredOpExecute.subst(enterxIop)
leavexCode = '''
- ArmISA::PCState pc = PCS;
- pc.nextThumb(true);
- pc.nextJazelle(false);
- PCS = pc;
+ NextThumb = true;
+ NextJazelle = false;
'''
leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
{ "code": leavexCode,
diff -r 9bd6b37d0189 -r 998b217dcae7 src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa Thu Dec 09 14:45:04 2010 -0800
+++ b/src/arch/arm/isa/operands.isa Thu Dec 09 14:45:17 2010 -0800
@@ -80,133 +80,178 @@
xc->%(func)s(this, %(op_idx)s, %(final_val)s);
}
'''
+
+ #PCState operands need to have a sorting index (the number at the end)
+ #less than all the integer registers which might update the PC. That way
+ #if the flag bits of the pc state are updated and a branch happens through
+ #R15, the updates are layered properly and the R15 update isn't lost.
+ srtNormal = 5
+ srtCpsr = 4
+ srtBase = 3
+ srtPC = 2
+ srtMode = 1
+ srtEPC = 0
+
+ def floatReg(idx):
+ return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
+
+ def intReg(idx):
+ return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
+ maybePCRead, maybePCWrite)
+
+ def intRegNPC(idx):
+ return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
+
+ def intRegAPC(idx, id = srtNormal):
+ return ('IntReg', 'uw', idx, 'IsInteger', id,
+ maybeAlignedPCRead, maybePCWrite)
+
+ def intRegIWPC(idx):
+ return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
+ maybePCRead, maybeIWPCWrite)
+
+ def intRegAIWPC(idx):
+ return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
+ maybePCRead, maybeAIWPCWrite)
+
+ def intRegCC(idx):
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