On Dec 16, 2010, at 1:30 PM, ziad abuowaimer wrote: > Hi All, > > My research idea is based on SMT for multicore processors so I need to > implement SMT on FS mode for OoO CPU. I looked to the FullO3CPU class > carefully and I have some questions that I think it will help me to implement > SMT on FS mode: > > Q1) At the beginning I want to fix the number of threads on each core for > example 2 or 4 for simplicity, but I need to know how I can assign the > software threads that generated from rcS file to a specific core and also to > a specific thread on that core later. I found in the archive that there is a > function called setAffinity() which is responsible for assigning loads to > cores I think so. My question is where I can find this function and is there > a way to look for a specific function in all src files. You can use the linux system call sched_setaffinity() emebedded in the code you're trying to run. Alternately, if you're trying to run a set of single threaded apps you can run m5 pin <progname> <args> and the m5 binary on the disk image will call sched_setaffinity() for you.
> Q2) I found in FullO3CPU: in FS mode one thread is created per core and it > does not assign a workload for that thread. (I understand that because of SMT > is not supported and only one thread is created but where that thread gets > its instructions from In full system mode the code cpus PC is set to the reset vector and it begins executing code. > > Q3) To support SMT on FS mode we need to wakeup a specific thread (we need to > pass tid to wakeup function). My question is where we call the wakeup(). I don't understand. > Q4) handling interrupts: right now checking interrupts is done only for > thread 0 and also interrupts processed or handled only by thread 0. And when > I checked the interrupt class I found a reference to cpu so we can match > specific interrupt to a specific cpu but not for a specific thread in that > cpu. My question is should I add a reference to tid (threadID) in the > interrupt class so that a related thread will only process that interrupt or > the interrupt can be handled by any thread running in that cpu. The CPU id in the interrupt controller probably should be named context id. It's not supposed to be for a CPU but a stream of execution. With a system with 1 CPU that has 2 threads the interrupt controller should interrupt "cpu" 0 and 1 as threads 0 and 1 on the SMT capable CPU. Ali > Correct me If I am in the wrong way. I appreciate your corrections, answers > and suggestions. > > thanks. > > Ziad. > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
