changeset 5d0f62927d75 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5d0f62927d75
description:
Style: Replace some tabs with spaces.
diffstat:
src/arch/SConscript | 2 +-
src/arch/alpha/isa/decoder.isa | 10 +-
src/arch/alpha/isa/fp.isa | 30 ++--
src/arch/alpha/isa/main.isa | 28 ++--
src/arch/alpha/isa/pal.isa | 8 +-
src/arch/arm/isa_traits.hh | 2 +-
src/arch/arm/linux/linux.cc | 50 ++++----
src/arch/arm/tlb.hh | 6 +-
src/arch/mips/SConscript | 6 +-
src/arch/mips/isa/bitfields.isa | 22 +-
src/arch/mips/isa/decoder.isa | 4 +-
src/arch/sparc/isa/base.isa | 2 +-
src/arch/sparc/isa/bitfields.isa | 72 ++++++------
src/arch/sparc/isa/formats/integerop.isa | 2 +-
src/arch/sparc/isa/operands.isa | 186 +++++++++++++++---------------
src/arch/x86/bios/SConscript | 4 +-
src/cpu/inorder/SConscript | 106 ++++++++--------
src/cpu/inorder/first_stage.hh | 2 +-
src/cpu/inorder/inorder_dyn_inst.hh | 30 ++--
src/cpu/inorder/resource.hh | 2 +-
src/cpu/inorder/resources/cache_unit.hh | 2 +-
src/dev/x86/cmos.cc | 8 +-
22 files changed, 292 insertions(+), 292 deletions(-)
diffs (truncated from 1021 to 300 lines):
diff -r 85e1847726e3 -r 5d0f62927d75 src/arch/SConscript
--- a/src/arch/SConscript Mon Dec 20 04:20:58 2010 -0500
+++ b/src/arch/SConscript Mon Dec 20 16:24:40 2010 -0500
@@ -45,7 +45,7 @@
isa_switch_hdrs = Split('''
faults.hh
interrupts.hh
- isa.hh
+ isa.hh
isa_traits.hh
kernel_stats.hh
locked_mem.hh
diff -r 85e1847726e3 -r 5d0f62927d75 src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa Mon Dec 20 04:20:58 2010 -0500
+++ b/src/arch/alpha/isa/decoder.isa Mon Dec 20 16:24:40 2010 -0500
@@ -100,7 +100,7 @@
format IntegerOperate {
- 0x10: decode INTFUNC { // integer arithmetic operations
+ 0x10: decode INTFUNC { // integer arithmetic operations
0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
0x40: addlv({{
@@ -173,7 +173,7 @@
}});
}
- 0x11: decode INTFUNC { // integer logical operations
+ 0x11: decode INTFUNC { // integer logical operations
0x00: and({{ Rc = Ra & Rb_or_imm; }});
0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
@@ -291,7 +291,7 @@
}});
}
- 0x13: decode INTFUNC { // integer multiplies
+ 0x13: decode INTFUNC { // integer multiplies
0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
0x30: umulh({{
@@ -301,7 +301,7 @@
}}, IntMultOp);
0x40: mullv({{
// 32-bit multiply with trap on overflow
- int64_t Rax = Ra.sl; // sign extended version of Ra.sl
+ int64_t Rax = Ra.sl; // sign extended version of Ra.sl
int64_t Rbx = Rb_or_imm.sl;
int64_t tmp = Rax * Rbx;
// To avoid overflow, all the upper 32 bits must match
@@ -587,7 +587,7 @@
format BasicOperateWithNopCheck {
0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
- 0x014: FailUnimpl::itoff(); // VAX-format conversion
+ 0x014: FailUnimpl::itoff(); // VAX-format conversion
}
}
}
diff -r 85e1847726e3 -r 5d0f62927d75 src/arch/alpha/isa/fp.isa
--- a/src/arch/alpha/isa/fp.isa Mon Dec 20 04:20:58 2010 -0500
+++ b/src/arch/alpha/isa/fp.isa Mon Dec 20 16:24:40 2010 -0500
@@ -32,9 +32,9 @@
//
// Floating-point instructions
//
-// Note that many FP-type instructions which do not support all the
-// various rounding & trapping modes use the simpler format
-// BasicOperateWithNopCheck.
+// Note that many FP-type instructions which do not support all the
+// various rounding & trapping modes use the simpler format
+// BasicOperateWithNopCheck.
//
output exec {{
@@ -45,7 +45,7 @@
#if FULL_SYSTEM
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
- Fault fault = NoFault; // dummy... this ipr access should not fault
+ Fault fault = NoFault; // dummy... this ipr access should not fault
if (!ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
fault = new FloatEnableFault;
}
@@ -71,11 +71,11 @@
public:
/// Alpha FP rounding modes.
enum RoundingMode {
- Chopped = 0, ///< round toward zero
+ Chopped = 0, ///< round toward zero
Minus_Infinity = 1, ///< round toward minus infinity
- Normal = 2, ///< round to nearest (default)
- Dynamic = 3, ///< use FPCR setting (in instruction)
- Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
+ Normal = 2, ///< round to nearest (default)
+ Dynamic = 3, ///< use FPCR setting (in instruction)
+ Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
};
/// Alpha FP trapping modes.
@@ -84,10 +84,10 @@
/// the assembly modifier is V rather than U.
enum TrappingMode {
/// default: nothing enabled
- Imprecise = 0, ///< no modifier
+ Imprecise = 0, ///< no modifier
/// underflow/overflow traps enabled, inexact disabled
- Underflow_Imprecise = 1, ///< /U or /V
- Underflow_Precise = 5, ///< /SU or /SV
+ Underflow_Imprecise = 1, ///< /U or /V
+ Underflow_Precise = 5, ///< /SU or /SV
/// underflow/overflow and inexact traps enabled
Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
};
@@ -192,10 +192,10 @@
}
const int AlphaFP::alphaToC99RoundingMode[] = {
- M5_FE_TOWARDZERO, // Chopped
- M5_FE_DOWNWARD, // Minus_Infinity
- M5_FE_TONEAREST, // Normal
- M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
+ M5_FE_TOWARDZERO, // Chopped
+ M5_FE_DOWNWARD, // Minus_Infinity
+ M5_FE_TONEAREST, // Normal
+ M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
};
const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
diff -r 85e1847726e3 -r 5d0f62927d75 src/arch/alpha/isa/main.isa
--- a/src/arch/alpha/isa/main.isa Mon Dec 20 04:20:58 2010 -0500
+++ b/src/arch/alpha/isa/main.isa Mon Dec 20 16:24:40 2010 -0500
@@ -102,30 +102,30 @@
// Universal (format-independent) fields
def bitfield PALMODE <32:32>;
-def bitfield OPCODE <31:26>;
-def bitfield RA <25:21>;
-def bitfield RB <20:16>;
+def bitfield OPCODE <31:26>;
+def bitfield RA <25:21>;
+def bitfield RB <20:16>;
// Memory format
def signed bitfield MEMDISP <15: 0>; // displacement
def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
// Memory-format jumps
-def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
-def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
+def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
+def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
// Branch format
def signed bitfield BRDISP <20: 0>; // displacement
// Integer operate format(s>;
-def bitfield INTIMM <20:13>; // integer immediate (literal)
-def bitfield IMM <12:12>; // immediate flag
-def bitfield INTFUNC <11: 5>; // function code
-def bitfield RC < 4: 0>; // dest reg
+def bitfield INTIMM <20:13>; // integer immediate (literal)
+def bitfield IMM <12:12>; // immediate flag
+def bitfield INTFUNC <11: 5>; // function code
+def bitfield RC < 4: 0>; // dest reg
// Floating-point operate format
-def bitfield FA <25:21>;
-def bitfield FB <20:16>;
+def bitfield FA <25:21>;
+def bitfield FB <20:16>;
def bitfield FP_FULLFUNC <15: 5>; // complete function code
def bitfield FP_TRAPMODE <15:13>; // trapping mode
def bitfield FP_ROUNDMODE <12:11>; // rounding mode
@@ -133,10 +133,10 @@
def bitfield FP_SRCTYPE <10: 9>; // source reg type
def bitfield FP_SHORTFUNC < 8: 5>; // short function code
def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
-def bitfield FC < 4: 0>; // dest reg
+def bitfield FC < 4: 0>; // dest reg
// PALcode format
-def bitfield PALFUNC <25: 0>; // function code
+def bitfield PALFUNC <25: 0>; // function code
// EV5 PAL instructions:
// HW_LD/HW_ST
@@ -154,7 +154,7 @@
def bitfield HW_REI_MBZ <13: 0>; // must be zero
// HW_MTPR/MW_MFPR
-def bitfield HW_IPR_IDX <15:0>; // IPR index
+def bitfield HW_IPR_IDX <15:0>; // IPR index
// M5 instructions
def bitfield M5FUNC <7:0>;
diff -r 85e1847726e3 -r 5d0f62927d75 src/arch/alpha/isa/pal.isa
--- a/src/arch/alpha/isa/pal.isa Mon Dec 20 04:20:58 2010 -0500
+++ b/src/arch/alpha/isa/pal.isa Mon Dec 20 16:24:40 2010 -0500
@@ -84,10 +84,10 @@
class CallPalBase : public AlphaStaticInst
{
protected:
- int palFunc; ///< Function code part of instruction
- int palOffset; ///< Target PC, offset from IPR_PAL_BASE
- bool palValid; ///< is the function code valid?
- bool palPriv; ///< is this call privileged?
+ int palFunc; ///< Function code part of instruction
+ int palOffset; ///< Target PC, offset from IPR_PAL_BASE
+ bool palValid; ///< is the function code valid?
+ bool palPriv; ///< is this call privileged?
/// Constructor.
CallPalBase(const char *mnem, ExtMachInst _machInst,
diff -r 85e1847726e3 -r 5d0f62927d75 src/arch/arm/isa_traits.hh
--- a/src/arch/arm/isa_traits.hh Mon Dec 20 04:20:58 2010 -0500
+++ b/src/arch/arm/isa_traits.hh Mon Dec 20 16:24:40 2010 -0500
@@ -99,7 +99,7 @@
// return a no-op instruction... used for instruction fetch faults
const ExtMachInst NoopMachInst = 0x00000000;
- const int LogVMPageSize = 12; // 4K bytes
+ const int LogVMPageSize = 12; // 4K bytes
const int VMPageSize = (1 << LogVMPageSize);
// Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
diff -r 85e1847726e3 -r 5d0f62927d75 src/arch/arm/linux/linux.cc
--- a/src/arch/arm/linux/linux.cc Mon Dec 20 04:20:58 2010 -0500
+++ b/src/arch/arm/linux/linux.cc Mon Dec 20 16:24:40 2010 -0500
@@ -36,49 +36,49 @@
// open(2) flags translation table
OpenFlagTransTable ArmLinux::openFlagTable[] = {
#ifdef _MSC_VER
- { ArmLinux::TGT_O_RDONLY, _O_RDONLY },
- { ArmLinux::TGT_O_WRONLY, _O_WRONLY },
- { ArmLinux::TGT_O_RDWR, _O_RDWR },
- { ArmLinux::TGT_O_APPEND, _O_APPEND },
- { ArmLinux::TGT_O_CREAT, _O_CREAT },
- { ArmLinux::TGT_O_TRUNC, _O_TRUNC },
- { ArmLinux::TGT_O_EXCL, _O_EXCL },
+ { ArmLinux::TGT_O_RDONLY, _O_RDONLY },
+ { ArmLinux::TGT_O_WRONLY, _O_WRONLY },
+ { ArmLinux::TGT_O_RDWR, _O_RDWR },
+ { ArmLinux::TGT_O_APPEND, _O_APPEND },
+ { ArmLinux::TGT_O_CREAT, _O_CREAT },
+ { ArmLinux::TGT_O_TRUNC, _O_TRUNC },
+ { ArmLinux::TGT_O_EXCL, _O_EXCL },
#ifdef _O_NONBLOCK
- { ArmLinux::TGT_O_NONBLOCK, _O_NONBLOCK },
+ { ArmLinux::TGT_O_NONBLOCK, _O_NONBLOCK },
#endif
#ifdef _O_NOCTTY
- { ArmLinux::TGT_O_NOCTTY, _O_NOCTTY },
+ { ArmLinux::TGT_O_NOCTTY, _O_NOCTTY },
#endif
#ifdef _O_SYNC
- { ArmLinux::TGT_O_SYNC, _O_SYNC },
+ { ArmLinux::TGT_O_SYNC, _O_SYNC },
#endif
#else /* !_MSC_VER */
- { ArmLinux::TGT_O_RDONLY, O_RDONLY },
- { ArmLinux::TGT_O_WRONLY, O_WRONLY },
- { ArmLinux::TGT_O_RDWR, O_RDWR },
- { ArmLinux::TGT_O_CREAT, O_CREAT },
- { ArmLinux::TGT_O_EXCL, O_EXCL },
- { ArmLinux::TGT_O_NOCTTY, O_NOCTTY },
- { ArmLinux::TGT_O_TRUNC, O_TRUNC },
- { ArmLinux::TGT_O_APPEND, O_APPEND },
- { ArmLinux::TGT_O_NONBLOCK, O_NONBLOCK },
+ { ArmLinux::TGT_O_RDONLY, O_RDONLY },
+ { ArmLinux::TGT_O_WRONLY, O_WRONLY },
+ { ArmLinux::TGT_O_RDWR, O_RDWR },
+ { ArmLinux::TGT_O_CREAT, O_CREAT },
+ { ArmLinux::TGT_O_EXCL, O_EXCL },
+ { ArmLinux::TGT_O_NOCTTY, O_NOCTTY },
+ { ArmLinux::TGT_O_TRUNC, O_TRUNC },
+ { ArmLinux::TGT_O_APPEND, O_APPEND },
+ { ArmLinux::TGT_O_NONBLOCK, O_NONBLOCK },
#ifdef O_SYNC
- { ArmLinux::TGT_O_SYNC, O_SYNC },
+ { ArmLinux::TGT_O_SYNC, O_SYNC },
#endif
#ifdef FASYNC
- { ArmLinux::TGT_FASYNC, FASYNC },
+ { ArmLinux::TGT_FASYNC, FASYNC },
#endif
#ifdef O_DIRECT
- { ArmLinux::TGT_O_DIRECT, O_DIRECT },
+ { ArmLinux::TGT_O_DIRECT, O_DIRECT },
#endif
#ifdef O_LARGEFILE
- { ArmLinux::TGT_O_LARGEFILE, O_LARGEFILE },
+ { ArmLinux::TGT_O_LARGEFILE, O_LARGEFILE },
#endif
#ifdef O_DIRECTORY
- { ArmLinux::TGT_O_DIRECTORY, O_DIRECTORY },
+ { ArmLinux::TGT_O_DIRECTORY, O_DIRECTORY },
#endif
#ifdef O_NOFOLLOW
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
