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Review request for Default. Summary ------- This patch changes the manner in which data is copied from L1 to L2 cache in the implementation of the Hammer's cache coherence protocol. Earlier, data was copied directly from one cache entry to another. This has been broken in to two parts. First, the data is copied from the source cache entry to a transaction buffer entry. Then, data is copied from the transaction buffer entry to the destination cache entry. This has been done to maintain the invariant - at any given instant, a multiple caches under a controller are exclusive with respect to each other. Diffs ----- src/mem/protocol/MOESI_hammer-cache.sm UNKNOWN Diff: http://reviews.m5sim.org/r/334/diff Testing ------- The changes have been tested with ruby random tester using a single seed for 100,000 loads and number of processors = 1, 2, 4 and 8. Thanks, Nilay
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