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(Updated 2011-01-06 07:29:17.470364) Review request for Default. Changes ------- This revision has following changes from the previous version - 1. The most important change is that we now formally assume that if multiple cache memories under the controller of a single controller, then for any given address, at most one of them can hold a cache entry for it. This simplifies a lot many things. We are now required to work with only one cache entry pointer. This pointer is set to the cache entry for the address being passed to the trigger function. The checks that have to carried out for code generation also get simplified. 2. is_invalid() has been introduced that can be used for testing whether a given entry (cache or transaction buffer) == NULL. 3. Earlier, *_ptr variables where being added on declaration of methods (which make use of TBE and / or Cache Entry), actions and in-ports. This is not being done any longer. 4. In FuncCallExprAST.py, when function parameters are passed to a function, a check has been added for expressions that are being passed as parameters. If the expression has a type TBE or AbstractCacheEntry, then all the occurrences of '*' are removed from the expression. This is under the assumption that the code from which the function call is being made has pointers to the variables being passed. Since SLICC will replace any occurrence of these variables with dereferenced version, therefore it is required that '*' be removed before the variable is passed to the function. Summary ------- The purpose of this patch is to change the way CacheMemory interfaces with coherence protocols. Currently, whenever a cache controller (defined in the protocol under consideration) needs to carry out any operation on a cache block, it looks up the tag hash map and figures out whether or not the block exists in the cache. In case it does exist, the operation is carried out (which requires another lookup). Over a single clock cycle, multiple such lookups take place as observed through profiling of different protocols. It was seen that the tag lookup takes anything from 10% to 20% of the simulation time. In order to reduce this time, this patch is being posted. The CacheMemory class now will have a function that will return pointer to a cache block entry, instead of a reference (though the function that returns the reference has been retained currently). Functions have been introduced for setting/unsetting a pointer and check its pointer. Similar changes have been carried out for Transaction Buffer entries as well. Note that changes are required to both SLICC and the protocol files. This patch carries out changes to SLICC and committing this patch alone, I believe, will ___break___ all the protocols. I am working on patching the protocols as well. This patch is being put to get feed back from other developers. Diffs (updated) ----- src/mem/ruby/slicc_interface/AbstractCacheEntry.hh UNKNOWN src/mem/ruby/slicc_interface/AbstractCacheEntry.cc UNKNOWN src/mem/ruby/system/CacheMemory.hh UNKNOWN src/mem/ruby/system/CacheMemory.cc UNKNOWN src/mem/ruby/system/TBETable.hh UNKNOWN src/mem/slicc/ast/ActionDeclAST.py UNKNOWN src/mem/slicc/ast/FormalParamAST.py UNKNOWN src/mem/slicc/ast/FuncCallExprAST.py UNKNOWN src/mem/slicc/ast/InPortDeclAST.py UNKNOWN src/mem/slicc/ast/MethodCallExprAST.py UNKNOWN src/mem/slicc/ast/TypeDeclAST.py UNKNOWN src/mem/slicc/ast/__init__.py UNKNOWN src/mem/slicc/parser.py UNKNOWN src/mem/slicc/symbols/StateMachine.py UNKNOWN src/mem/protocol/RubySlicc_Types.sm UNKNOWN Diff: http://reviews.m5sim.org/r/358/diff Testing ------- I have tested these changes using the MOESI_CMP_directory and MI protocols. Thanks, Nilay
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