changeset a82dcad2bc18 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=a82dcad2bc18 description: Regression Tests: Update the output for MESI_CMP_directory This patch updates the output for regression tests that are carried out on MESI_CMP_directory protocol. The changes made to the protocol in order to remove the bugs present result in regression failure for the 60.rubytest. Since the earlier protocol was incorrect, so we certainly cannot relay on the earlier reference output. Hence, the update.
diffstat: tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini | 54 +- tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats | 63 +- tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout | 8 +- tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt | 8 +- tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini | 54 +- tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats | 61 +- tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout | 8 +- tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt | 8 +- tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini | 11 +- tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats | 37 +- tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout | 8 +- tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt | 6 +- tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini | 57 +- tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats | 399 +++++---- tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout | 10 +- tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt | 10 +- 16 files changed, 399 insertions(+), 403 deletions(-) diffs (truncated from 1485 to 300 lines): diff -r 8f37a23e02d7 -r a82dcad2bc18 tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini Thu Jan 13 22:17:11 2011 -0600 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini Thu Jan 13 22:48:03 2011 -0600 @@ -32,8 +32,8 @@ system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -109,34 +109,21 @@ [system.l1_cntrl0] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports to_l2_latency=1 transitions_per_cycle=32 version=0 -[system.l1_cntrl0.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.l1_cntrl0.sequencer.dcache -deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.l1_cntrl0.sequencer.dcache] +[system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 latency=3 @@ -144,7 +131,7 @@ size=256 start_index_bit=6 -[system.l1_cntrl0.sequencer.icache] +[system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -181,14 +168,13 @@ null=false range=0:134217727 zero=false -port=system.l1_cntrl0.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -198,13 +184,17 @@ stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port [system.ruby.network] type=SimpleNetwork @@ -220,9 +210,9 @@ [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -name=Crossbar num_int_nodes=4 print_config=false diff -r 8f37a23e02d7 -r a82dcad2bc18 tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats Thu Jan 13 22:17:11 2011 -0600 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats Thu Jan 13 22:48:03 2011 -0600 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,27 +34,27 @@ ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 10:23:43 +Real time: Jan/13/2011 22:36:30 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 2 +Elapsed_time_in_minutes: 0.0333333 +Elapsed_time_in_hours: 0.000555556 +Elapsed_time_in_days: 2.31481e-05 -Virtual_time_in_seconds: 0.32 -Virtual_time_in_minutes: 0.00533333 -Virtual_time_in_hours: 8.88889e-05 -Virtual_time_in_days: 3.7037e-06 +Virtual_time_in_seconds: 1.2 +Virtual_time_in_minutes: 0.02 +Virtual_time_in_hours: 0.000333333 +Virtual_time_in_days: 1.38889e-05 Ruby_current_time: 275313 Ruby_start_time: 0 Ruby_cycles: 275313 -mbytes_resident: 34.8867 -mbytes_total: 34.8945 -resident_ratio: 1 +mbytes_resident: 22.0195 +mbytes_total: 156.82 +resident_ratio: 0.140462 ruby_cycles_executed: [ 275314 ] @@ -117,10 +117,10 @@ Resource Usage -------------- page_size: 4096 -user_time: 0 +user_time: 1 system_time: 0 -page_reclaims: 7576 -page_faults: 2166 +page_reclaims: 6300 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -197,20 +197,20 @@ outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 0 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 -Cache Stats: system.l1_cntrl0.sequencer.dcache - system.l1_cntrl0.sequencer.dcache_total_misses: 0 - system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 - system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 --- L1Cache --- @@ -318,6 +318,13 @@ E_I Store [0 ] 0 E_I L1_Replacement [0 ] 0 +SINK_WB_ACK Load [0 ] 0 +SINK_WB_ACK Ifetch [0 ] 0 +SINK_WB_ACK Store [0 ] 0 +SINK_WB_ACK Inv [0 ] 0 +SINK_WB_ACK L1_Replacement [0 ] 0 +SINK_WB_ACK WB_Ack [0 ] 0 + Cache Stats: system.l2_cntrl0.L2cacheMemory system.l2_cntrl0.L2cacheMemory_total_misses: 0 system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 diff -r 8f37a23e02d7 -r a82dcad2bc18 tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout Thu Jan 13 22:17:11 2011 -0600 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout Thu Jan 13 22:48:03 2011 -0600 @@ -5,10 +5,10 @@ All Rights Reserved -M5 compiled Aug 5 2010 10:22:52 -M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip -M5 started Aug 5 2010 10:23:42 -M5 executing on svvint09 +M5 compiled Jan 13 2011 22:36:25 +M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip +M5 started Jan 13 2011 22:36:28 +M5 executing on scamorza.cs.wisc.edu command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff -r 8f37a23e02d7 -r a82dcad2bc18 tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt Thu Jan 13 22:17:11 2011 -0600 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt Thu Jan 13 22:48:03 2011 -0600 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 24630 # Simulator instruction rate (inst/s) -host_mem_usage 212388 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host -host_tick_rate 1058851 # Simulator tick rate (ticks/s) +host_inst_rate 4080 # Simulator instruction rate (inst/s) +host_mem_usage 160588 # Number of bytes of host memory used +host_seconds 1.57 # Real time elapsed on the host +host_tick_rate 175338 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000275 # Number of seconds simulated diff -r 8f37a23e02d7 -r a82dcad2bc18 tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini Thu Jan 13 22:17:11 2011 -0600 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini Thu Jan 13 22:48:03 2011 -0600 @@ -32,8 +32,8 @@ system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -109,34 +109,21 @@ [system.l1_cntrl0] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory buffer_size=0 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports to_l2_latency=1 transitions_per_cycle=32 version=0 _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev