changeset 696063d6ed04 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=696063d6ed04
description:
SPARC: Update stats for the call r15 as source change.
diffstat:
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout |
10 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt |
364 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout |
10 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt |
522 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout |
54 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt |
2469 +++++----
6 files changed, 1715 insertions(+), 1714 deletions(-)
diffs (truncated from 4289 to 300 lines):
diff -r bd474b97535c -r 696063d6ed04
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout Sat Jan 15
15:30:17 2011 -0800
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout Sat Jan 15
15:30:34 2011 -0800
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled Dec 2 2010 15:11:52
-M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase
-M5 started Dec 3 2010 12:08:56
-M5 executing on zizzer
+M5 compiled Jan 15 2011 04:38:18
+M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip
+M5 started Jan 15 2011 04:38:23
+M5 executing on tater
command line: build/SPARC_SE/m5.fast -d
build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py
build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -43,4 +43,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 601459170500 because target called exit()
+Exiting @ tick 601459117000 because target called exit()
diff -r bd474b97535c -r 696063d6ed04
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt Sat Jan 15
15:30:17 2011 -0800
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt Sat Jan 15
15:30:34 2011 -0800
@@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 193964 #
Simulator instruction rate (inst/s)
-host_mem_usage 208068 #
Number of bytes of host memory used
-host_seconds 7246.73 #
Real time elapsed on the host
-host_tick_rate 82997346 #
Simulator tick rate (ticks/s)
+host_inst_rate 115319 #
Simulator instruction rate (inst/s)
+host_mem_usage 220936 #
Number of bytes of host memory used
+host_seconds 12188.85 #
Real time elapsed on the host
+host_tick_rate 49345009 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 1405604152 #
Number of instructions simulated
sim_seconds 0.601459 #
Number of seconds simulated
-sim_ticks 601459170500 #
Number of ticks simulated
+sim_ticks 601459117000 #
Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 98804477 #
Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 100538318 #
Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 98804472 #
Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 100538302 #
Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 #
Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 5348297 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 105813048 #
Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 105813048 #
Number of BP lookups
+system.cpu.BPredUnit.condPredicted 105813027 #
Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 105813027 #
Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 #
Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 86248929 #
Number of branches committed
-system.cpu.commit.COM:bw_lim_events 21327804 #
number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 21327805 #
number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 1172142474
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 1172142381
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.270770
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.680117
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 418030495 35.66%
35.66% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 498323128 42.51%
78.18% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 52996990 4.52%
82.70% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 103673808 8.84%
91.54% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 418030405 35.66%
35.66% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 498323124 42.51%
78.18% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 52996988 4.52%
82.70% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 103673812 8.84%
91.54% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 32915552 2.81%
94.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 8294277 0.71%
95.06% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 8294276 0.71%
95.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 25634202 2.19%
97.25% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 10946218 0.93%
98.18% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 21327804 1.82%
100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 10946217 0.93%
98.18% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 21327805 1.82%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 1172142474
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 1172142381
# Number of insts commited each cycle
system.cpu.commit.COM:count 1489523295 #
Number of instructions committed
system.cpu.commit.COM:loads 402512844 #
Number of loads committed
system.cpu.commit.COM:membars 51356 #
Number of memory barriers committed
@@ -44,22 +44,22 @@
system.cpu.commit.branchMispredicts 5348297 #
The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489523295 #
The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243671 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 219358956 #
The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 219358890 #
The number of squashed insts skipped by commit
system.cpu.committedInsts 1405604152 #
Number of Instructions Simulated
system.cpu.committedInsts_total 1405604152 #
Number of Instructions Simulated
system.cpu.cpi 0.855802 #
CPI: Cycles Per Instruction
system.cpu.cpi_total 0.855802 #
CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 295702053 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14658.341236
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.553744
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_accesses 295702052 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14658.314544
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.427114
# average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 294883757 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 11994862000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 11994825500 #
number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002767 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 818296 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_misses 818295 #
number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 604804 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1593836000
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 1593801500
# number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000722 #
mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 213492 #
number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses 213491 #
number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 #
number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 38142.857143
# average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35142.857143
# average SwapReq mshr miss latency
@@ -83,127 +83,127 @@
system.cpu.dcache.WriteReq_mshr_misses 268065 #
number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 955.149583 #
Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 955.151567 #
Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 462548869 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 15269.190131 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 10449.986812
# average overall mshr miss latency
+system.cpu.dcache.demand_accesses 462548868 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 15269.181916 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 10449.936869
# average overall mshr miss latency
system.cpu.dcache.demand_hits 459964335 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 39463741045 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 39463704545 #
number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005588 #
miss rate for demand accesses
-system.cpu.dcache.demand_misses 2584534 #
number of demand (read+write) misses
+system.cpu.dcache.demand_misses 2584533 #
number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2102977 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5032264299
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 5032229799
# number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.001041 #
mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 481557 #
number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 481556 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999859 #
Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4095.424423 #
Average occupied blocks per context
-system.cpu.dcache.overall_accesses 462548869 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 15269.190131
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 10449.986812
# average overall mshr miss latency
+system.cpu.dcache.occ_blocks::0 4095.424477 #
Average occupied blocks per context
+system.cpu.dcache.overall_accesses 462548868 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 15269.181916
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 10449.936869
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 459964335 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 39463741045 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 39463704545 #
number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005588 #
miss rate for overall accesses
-system.cpu.dcache.overall_misses 2584534 #
number of overall misses
+system.cpu.dcache.overall_misses 2584533 #
number of overall misses
system.cpu.dcache.overall_mshr_hits 2102977 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5032264299
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 5032229799
# number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.001041 #
mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 481557 #
number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 481556 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 477468 #
number of replacements
-system.cpu.dcache.sampled_refs 481564 #
Sample count of references to valid blocks.
+system.cpu.dcache.replacements 477467 #
number of replacements
+system.cpu.dcache.sampled_refs 481563 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.424423 #
Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4095.424477 #
Cycle average of tags in use
system.cpu.dcache.total_refs 459965654 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 132275000 #
Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 428419 #
number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 393632662 #
Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 1750743114 #
Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 405697797 #
Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 351108016 #
Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 30410707 #
Number of cycles decode is squashing
+system.cpu.dcache.warmup_cycle 132267000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 428418 #
number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 393632591 #
Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 1750743071 #
Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 405697785 #
Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 351108006 #
Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 30410701 #
Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 21703388 #
Number of cycles decode is unblocking
-system.cpu.fetch.Branches 105813048 #
Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 173096808 #
Number of cache lines fetched
-system.cpu.fetch.Cycles 548235409 #
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 1429410 #
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 1755979749 #
Number of instructions fetch has processed
+system.cpu.fetch.Branches 105813027 #
Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 173096803 #
Number of cache lines fetched
+system.cpu.fetch.Cycles 548235394 #
Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1429408 #
Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 1755979705 #
Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 6170644 #
Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.087964 #
Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 173096808 #
Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 98804477 #
Number of branches that fetch has predicted taken
+system.cpu.fetch.icacheStallCycles 173096803 #
Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 98804472 #
Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.459766 #
Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 1202552570 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 1202552471 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.464003 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.699994 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 827414016 68.80% 68.80% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 82887160 6.89% 75.70% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 45822502 3.81% 79.51% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22740112 1.89% 81.40% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 827413927 68.80% 68.80% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 82887157 6.89% 75.70% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 45822503 3.81% 79.51% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22740108 1.89% 81.40% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 33832197 2.81% 84.21% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 32824408 2.73% 86.94% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 14992288 1.25% 88.19% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 32824411 2.73% 86.94% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 14992283 1.25% 88.19% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7935666 0.66% 88.85% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 134104221 11.15% 100.00% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 134104219 11.15% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1202552570 #
Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 173096808 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35071.906355
# average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35057.573416
# average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 173095014 #
number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 62919000 #
number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total 1202552471 #
Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 173096803 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35063.545151
# average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35058.732612
# average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 173095009 #
number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 62904000 #
number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000010 #
miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1794 #
number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 500 #
number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 45364500
# number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 45366000
# number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 #
mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1294 #
number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.icache.avg_refs 133870.853828 #
Average number of references to valid blocks.
+system.cpu.icache.avg_refs 133870.849961 #
Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.icache.cache_copies 0 #
number of cache copies performed
-system.cpu.icache.demand_accesses 173096808 #
number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35071.906355 #
average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35057.573416
# average overall mshr miss latency
-system.cpu.icache.demand_hits 173095014 #
number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 62919000 #
number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 173096803 #
number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35063.545151 #
average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35058.732612
# average overall mshr miss latency
+system.cpu.icache.demand_hits 173095009 #
number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 62904000 #
number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000010 #
miss rate for demand accesses
system.cpu.icache.demand_misses 1794 #
number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 500 #
number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 45364500
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 45366000
# number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000007 #
mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1294 #
number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.509485 #
Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1043.425077 #
Average occupied blocks per context
-system.cpu.icache.overall_accesses 173096808 #
number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35071.906355
# average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35057.573416
# average overall mshr miss latency
+system.cpu.icache.occ_blocks::0 1043.425085 #
Average occupied blocks per context
+system.cpu.icache.overall_accesses 173096803 #
number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35063.545151
# average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35058.732612
# average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 173095014 #
number of overall hits
-system.cpu.icache.overall_miss_latency 62919000 #
number of overall miss cycles
+system.cpu.icache.overall_hits 173095009 #
number of overall hits
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