changeset cc5e64f8423f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cc5e64f8423f
description:
ARM: Add support for moving predicated false dest operands from sources.
diffstat:
src/arch/arm/isa/insts/misc.isa | 3 +-
src/arch/arm/isa/templates/basic.isa | 5 ++
src/arch/arm/isa/templates/branch.isa | 30 +++++++++++++++
src/arch/arm/isa/templates/macromem.isa | 60 ++++++++++++++++++++++++++++++
src/arch/arm/isa/templates/mem.isa | 60 ++++++++++++++++++++++++++++++
src/arch/arm/isa/templates/misc.isa | 65 +++++++++++++++++++++++++++++++++
src/arch/arm/isa/templates/mult.isa | 10 +++++
src/arch/arm/isa/templates/neon.isa | 25 ++++++++++++
src/arch/arm/isa/templates/pred.isa | 15 +++++++
src/arch/arm/isa/templates/vfp.isa | 20 ++++++++++
src/arch/arm/registers.hh | 6 ++-
src/cpu/o3/dyn_inst.hh | 12 ++++++
src/cpu/o3/iew_impl.hh | 2 +
src/cpu/o3/lsq_unit_impl.hh | 5 ++
14 files changed, 315 insertions(+), 3 deletions(-)
diffs (truncated from 805 to 300 lines):
diff -r 0c6613ad8f18 -r cc5e64f8423f src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa Tue Jan 18 16:30:01 2011 -0600
+++ b/src/arch/arm/isa/insts/misc.isa Tue Jan 18 16:30:02 2011 -0600
@@ -467,8 +467,7 @@
exec_output += PredOpExecute.subst(usada8Iop)
bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
- bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
- bkptCode)
+ bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
header_output += BasicDeclare.subst(bkptIop)
decoder_output += BasicConstructor.subst(bkptIop)
exec_output += BasicExecute.subst(bkptIop)
diff -r 0c6613ad8f18 -r cc5e64f8423f src/arch/arm/isa/templates/basic.isa
--- a/src/arch/arm/isa/templates/basic.isa Tue Jan 18 16:30:01 2011 -0600
+++ b/src/arch/arm/isa/templates/basic.isa Tue Jan 18 16:30:02 2011 -0600
@@ -52,6 +52,11 @@
inline %(class_name)s::%(class_name)s(ExtMachInst machInst) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
diff -r 0c6613ad8f18 -r cc5e64f8423f src/arch/arm/isa/templates/branch.isa
--- a/src/arch/arm/isa/templates/branch.isa Tue Jan 18 16:30:01 2011 -0600
+++ b/src/arch/arm/isa/templates/branch.isa Tue Jan 18 16:30:02 2011 -0600
@@ -53,6 +53,11 @@
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -75,6 +80,11 @@
_imm, _condCode)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -94,6 +104,11 @@
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -116,6 +131,11 @@
_op1, _condCode)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -152,6 +172,11 @@
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -173,5 +198,10 @@
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
diff -r 0c6613ad8f18 -r cc5e64f8423f src/arch/arm/isa/templates/macromem.isa
--- a/src/arch/arm/isa/templates/macromem.isa Tue Jan 18 16:30:01 2011 -0600
+++ b/src/arch/arm/isa/templates/macromem.isa Tue Jan 18 16:30:02 2011 -0600
@@ -69,6 +69,11 @@
_ura, _urb, _up, _imm)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -89,6 +94,11 @@
{
memAccessFlags |= extraMemFlags;
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
%(BasicExecDeclare)s
@@ -121,6 +131,11 @@
_ura, _urb, _urc)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -158,6 +173,11 @@
_dest, _op1, _step)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
%(BasicExecDeclare)s
@@ -208,6 +228,11 @@
_dest, _op1, _step, _lane)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
%(BasicExecDeclare)s
@@ -236,6 +261,11 @@
_ura, _urb)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -264,6 +294,11 @@
_ura, _urb, _imm)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -286,6 +321,11 @@
_ura, _urb, _urc, _shiftAmt, _shiftType)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -317,6 +357,11 @@
index, up, user, writeback, load, reglist)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -341,6 +386,11 @@
rn, vd, regs, inc, size, align, rm)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -364,6 +414,11 @@
rn, vd, regs, inc, size, align, rm, lane)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -390,6 +445,11 @@
vd, single, up, writeback, load, offset)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
diff -r 0c6613ad8f18 -r cc5e64f8423f src/arch/arm/isa/templates/mem.isa
--- a/src/arch/arm/isa/templates/mem.isa Tue Jan 18 16:30:01 2011 -0600
+++ b/src/arch/arm/isa/templates/mem.isa Tue Jan 18 16:30:02 2011 -0600
@@ -913,6 +913,11 @@
(IntRegIndex)_base, (AddrMode)_mode, _wb)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
#if %(use_uops)d
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
@@ -931,6 +936,11 @@
(OperatingMode)_regMode, (AddrMode)_mode, _wb)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
#if %(use_uops)d
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
@@ -949,6 +959,11 @@
(IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -961,6 +976,11 @@
(IntRegIndex)_base, _add, _imm)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
#if %(use_uops)d
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
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