[m5-dev] changeset in m5: O3: Fixes the way prefetches are handled inside...

[Matt Horsnell]

changeset 02450f4443ce in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=02450f4443ce
description:
        O3: Fixes the way prefetches are handled inside the iew unit.

        This patch prevents the prefetch being added to the instCommit queue 
twice.

diffstat:

 src/arch/arm/faults.hh |  3 ++-
 src/arch/arm/tlb.cc    |  8 +++++++-
 src/cpu/o3/iew_impl.hh |  6 ++++--
 3 files changed, 13 insertions(+), 4 deletions(-)

diffs (56 lines):

diff -r 2290428b5f04 -r 02450f4443ce src/arch/arm/faults.hh
--- a/src/arch/arm/faults.hh    Tue Jan 18 16:30:02 2011 -0600
+++ b/src/arch/arm/faults.hh    Tue Jan 18 16:30:02 2011 -0600
@@ -92,7 +92,8 @@
         // to allow the translation function to inform
         // the memory access function not to proceed
         // for a Prefetch that misses in the TLB.
-        PrefetchTLBMiss
+        PrefetchTLBMiss = 0x1f,
+        PrefetchUncacheable = 0x20
     };
 
     struct FaultVals
diff -r 2290428b5f04 -r 02450f4443ce src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc       Tue Jan 18 16:30:02 2011 -0600
+++ b/src/arch/arm/tlb.cc       Tue Jan 18 16:30:02 2011 -0600
@@ -556,9 +556,15 @@
             outerAttrs: %d\n",
             te->shareable, te->innerAttrs, te->outerAttrs);
     setAttr(te->attributes);
-    if (te->nonCacheable)
+    if (te->nonCacheable) {
         req->setFlags(Request::UNCACHEABLE);
 
+        // Prevent prefetching from I/O devices.
+        if (req->isPrefetch()) {
+            return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable);
+        }
+    }
+
     switch ( (dacr >> (te->domain * 2)) & 0x3) {
       case 0:
         domainFaults++;
diff -r 2290428b5f04 -r 02450f4443ce src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh    Tue Jan 18 16:30:02 2011 -0600
+++ b/src/cpu/o3/iew_impl.hh    Tue Jan 18 16:30:02 2011 -0600
@@ -1222,8 +1222,7 @@
         // Execute instruction.
         // Note that if the instruction faults, it will be handled
         // at the commit stage.
-        if (inst->isMemRef() &&
-            (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
+        if (inst->isMemRef()) {
             DPRINTF(IEW, "Execute: Calculating address for memory "
                     "reference.\n");
 
@@ -1232,6 +1231,9 @@
                 // Loads will mark themselves as executed, and their writeback
                 // event adds the instruction to the queue to commit
                 fault = ldstQueue.executeLoad(inst);
+                if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
+                    fault = NoFault;
+                }
             } else if (inst->isStore()) {
                 fault = ldstQueue.executeStore(inst);
 
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