changeset 69aae4379062 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=69aae4379062
description:
ARM: The ARM decoder should not panic when decoding undefined holes is
arch.
This can abort simulations when the fetch unit runs ahead and
speculatively
decodes instructions that are off the execution path.
diffstat:
src/arch/arm/insts/macromem.cc | 50 ++++++++++++++++-------
src/arch/arm/insts/pred_inst.hh | 8 ++-
src/arch/arm/isa/formats/fp.isa | 10 ++++-
src/arch/arm/isa/formats/misc.isa | 5 +-
src/arch/arm/isa/insts/neon.isa | 79 ++++++++++++++++++++++++++------------
src/arch/arm/miscregs.cc | 2 -
6 files changed, 105 insertions(+), 49 deletions(-)
diffs (truncated from 354 to 300 lines):
diff -r 07ba4754ae0a -r 69aae4379062 src/arch/arm/insts/macromem.cc
--- a/src/arch/arm/insts/macromem.cc Tue Jan 18 16:30:05 2011 -0600
+++ b/src/arch/arm/insts/macromem.cc Tue Jan 18 16:30:05 2011 -0600
@@ -42,7 +42,9 @@
#include "arch/arm/insts/macromem.hh"
#include "arch/arm/decoder.hh"
+#include <sstream>
+using namespace std;
using namespace ArmISAInst;
namespace ArmISA
@@ -180,7 +182,8 @@
size, machInst, rMid, rn, 0, align);
break;
default:
- panic("Unrecognized number of registers %d.\n", regs);
+ // Unknown number of registers
+ microOps[uopIdx++] = new Unknown(machInst);
}
if (wb) {
if (rm != 15 && rm != 13) {
@@ -216,7 +219,8 @@
}
break;
default:
- panic("Bad number of elements to deinterleave %d.\n", elems);
+ // Bad number of elements to deinterleave
+ microOps[uopIdx++] = new Unknown(machInst);
}
}
assert(uopIdx == numMicroops);
@@ -315,7 +319,8 @@
machInst, ufp0, rn, 0, align);
break;
default:
- panic("Unrecognized load size %d.\n", regs);
+ // Unrecognized load size
+ microOps[uopIdx++] = new Unknown(machInst);
}
if (wb) {
if (rm != 15 && rm != 13) {
@@ -358,7 +363,8 @@
}
break;
default:
- panic("Bad size %d.\n", size);
+ // Bad size
+ microOps[uopIdx++] = new Unknown(machInst);
break;
}
break;
@@ -393,7 +399,8 @@
}
break;
default:
- panic("Bad size %d.\n", size);
+ // Bad size
+ microOps[uopIdx++] = new Unknown(machInst);
break;
}
break;
@@ -429,7 +436,8 @@
}
break;
default:
- panic("Bad size %d.\n", size);
+ // Bad size
+ microOps[uopIdx++] = new Unknown(machInst);
break;
}
break;
@@ -472,13 +480,15 @@
}
break;
default:
- panic("Bad size %d.\n", size);
+ // Bad size
+ microOps[uopIdx++] = new Unknown(machInst);
break;
}
}
break;
default:
- panic("Bad number of elements to unpack %d.\n", elems);
+ // Bad number of elements to unpack
+ microOps[uopIdx++] = new Unknown(machInst);
}
assert(uopIdx == numMicroops);
@@ -536,7 +546,8 @@
}
break;
default:
- panic("Bad number of elements to interleave %d.\n", elems);
+ // Bad number of elements to interleave
+ microOps[uopIdx++] = new Unknown(machInst);
}
}
switch (regs) {
@@ -561,7 +572,8 @@
size, machInst, rMid, rn, 0, align);
break;
default:
- panic("Unrecognized number of registers %d.\n", regs);
+ // Unknown number of registers
+ microOps[uopIdx++] = new Unknown(machInst);
}
if (wb) {
if (rm != 15 && rm != 13) {
@@ -627,7 +639,8 @@
machInst, ufp0, vd * 2, inc * 2, lane);
break;
default:
- panic("Bad size %d.\n", size);
+ // Bad size
+ microOps[uopIdx++] = new Unknown(machInst);
break;
}
break;
@@ -647,7 +660,8 @@
machInst, ufp0, vd * 2, inc * 2, lane);
break;
default:
- panic("Bad size %d.\n", size);
+ // Bad size
+ microOps[uopIdx++] = new Unknown(machInst);
break;
}
break;
@@ -668,7 +682,8 @@
machInst, ufp0, vd * 2, inc * 2, lane);
break;
default:
- panic("Bad size %d.\n", size);
+ // Bad size
+ microOps[uopIdx++] = new Unknown(machInst);
break;
}
break;
@@ -690,13 +705,15 @@
machInst, ufp0, (vd + offset) * 2, inc * 2, lane);
break;
default:
- panic("Bad size %d.\n", size);
+ // Bad size
+ microOps[uopIdx++] = new Unknown(machInst);
break;
}
}
break;
default:
- panic("Bad number of elements to pack %d.\n", elems);
+ // Bad number of elements to unpack
+ microOps[uopIdx++] = new Unknown(machInst);
}
switch (storeSize) {
case 1:
@@ -757,7 +774,8 @@
machInst, ufp0, rn, 0, align);
break;
default:
- panic("Unrecognized store size %d.\n", regs);
+ // Bad store size
+ microOps[uopIdx++] = new Unknown(machInst);
}
if (wb) {
if (rm != 15 && rm != 13) {
diff -r 07ba4754ae0a -r 69aae4379062 src/arch/arm/insts/pred_inst.hh
--- a/src/arch/arm/insts/pred_inst.hh Tue Jan 18 16:30:05 2011 -0600
+++ b/src/arch/arm/insts/pred_inst.hh Tue Jan 18 16:30:05 2011 -0600
@@ -78,9 +78,10 @@
}
static inline uint64_t
-simd_modified_imm(bool op, uint8_t cmode, uint8_t data)
+simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid)
{
uint64_t bigData = data;
+ immValid = true;
switch (cmode) {
case 0x0:
case 0x1:
@@ -139,9 +140,10 @@
bigData |= (bigData << 32);
break;
}
- // Fall through
+ // Fall through, immediate encoding is invalid.
default:
- panic("Illegal modified SIMD immediate parameters.\n");
+ immValid = false;
+ break;
}
return bigData;
}
diff -r 07ba4754ae0a -r 69aae4379062 src/arch/arm/isa/formats/fp.isa
--- a/src/arch/arm/isa/formats/fp.isa Tue Jan 18 16:30:05 2011 -0600
+++ b/src/arch/arm/isa/formats/fp.isa Tue Jan 18 16:30:05 2011 -0600
@@ -758,7 +758,15 @@
bits(machInst, 24)) << 7) |
(bits(machInst, 18, 16) << 4) |
(bits(machInst, 3, 0) << 0);
- const uint64_t bigImm = simd_modified_imm(op, cmode, imm);
+
+ // Check for invalid immediate encodings and return an unknown op
+ // if it happens
+ bool immValid = true;
+ const uint64_t bigImm = simd_modified_imm(op, cmode, imm, immValid);
+ if (!immValid) {
+ return new Unknown(machInst);
+ }
+
if (op) {
if (bits(cmode, 3) == 0) {
if (bits(cmode, 0) == 0) {
diff -r 07ba4754ae0a -r 69aae4379062 src/arch/arm/isa/formats/misc.isa
--- a/src/arch/arm/isa/formats/misc.isa Tue Jan 18 16:30:05 2011 -0600
+++ b/src/arch/arm/isa/formats/misc.isa Tue Jan 18 16:30:05 2011 -0600
@@ -100,7 +100,10 @@
case MISCREG_NOP:
return new NopInst(machInst);
case NUM_MISCREGS:
- return new Unknown(machInst);
+ return new FailUnimplemented(
+ csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s
unknown",
+ crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
+ machInst);
case MISCREG_DCCISW:
return new WarnUnimplemented(
isRead ? "mrc dccisw" : "mcr dcisw", machInst);
diff -r 07ba4754ae0a -r 69aae4379062 src/arch/arm/isa/insts/neon.isa
--- a/src/arch/arm/isa/insts/neon.isa Tue Jan 18 16:30:05 2011 -0600
+++ b/src/arch/arm/isa/insts/neon.isa Tue Jan 18 16:30:05 2011 -0600
@@ -871,14 +871,21 @@
if readDest:
readDestCode = 'destElem = gtoh(destReg.elements[i]);'
eWalkCode += '''
- assert(imm >= 0 && imm < eCount);
- for (unsigned i = 0; i < eCount; i++) {
- Element srcElem1 = gtoh(srcReg1.elements[i]);
- Element srcElem2 = gtoh(srcReg2.elements[imm]);
- Element destElem;
- %(readDest)s
- %(op)s
- destReg.elements[i] = htog(destElem);
+ if (imm < 0 && imm >= eCount) {
+#if FULL_SYSTEM
+ fault = new UndefinedInstruction;
+#else
+ fault = new UndefinedInstruction(false, mnemonic);
+#endif
+ } else {
+ for (unsigned i = 0; i < eCount; i++) {
+ Element srcElem1 = gtoh(srcReg1.elements[i]);
+ Element srcElem2 = gtoh(srcReg2.elements[imm]);
+ Element destElem;
+ %(readDest)s
+ %(op)s
+ destReg.elements[i] = htog(destElem);
+ }
}
''' % { "op" : op, "readDest" : readDestCode }
for reg in range(rCount):
@@ -919,14 +926,21 @@
if readDest:
readDestCode = 'destElem = gtoh(destReg.elements[i]);'
eWalkCode += '''
- assert(imm >= 0 && imm < eCount);
- for (unsigned i = 0; i < eCount; i++) {
- Element srcElem1 = gtoh(srcReg1.elements[i]);
- Element srcElem2 = gtoh(srcReg2.elements[imm]);
- BigElement destElem;
- %(readDest)s
- %(op)s
- destReg.elements[i] = htog(destElem);
+ if (imm < 0 && imm >= eCount) {
+#if FULL_SYSTEM
+ fault = new UndefinedInstruction;
+#else
+ fault = new UndefinedInstruction(false, mnemonic);
+#endif
+ } else {
+ for (unsigned i = 0; i < eCount; i++) {
+ Element srcElem1 = gtoh(srcReg1.elements[i]);
+ Element srcElem2 = gtoh(srcReg2.elements[imm]);
+ BigElement destElem;
+ %(readDest)s
+ %(op)s
+ destReg.elements[i] = htog(destElem);
+ }
}
''' % { "op" : op, "readDest" : readDestCode }
for reg in range(2 * rCount):
@@ -965,14 +979,21 @@
if readDest:
readDestCode = 'destReg = destRegs[i];'
eWalkCode += '''
- assert(imm >= 0 && imm < rCount);
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