changeset c0be563517da in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c0be563517da
description:
O3: Keep around the last committed instruction and use for squashing.
Without this change 0 is always used for the youngest sequence number if
a squash occured and the ROB was empty (E.g. an instruction is marked
serializeAfter or a fetch stall prevents other instructions from
issuing).
Using 0 there is a race to rename where an instruction that committed
the
same cycle as the squashing instruction can have it's renamed state
undone
by the squash using sequence number 0.
diffstat:
src/cpu/o3/commit.hh | 15 +++++++++++++++
src/cpu/o3/commit_impl.hh | 8 ++++++--
2 files changed, 21 insertions(+), 2 deletions(-)
diffs (66 lines):
diff -r 3c6783497976 -r c0be563517da src/cpu/o3/commit.hh
--- a/src/cpu/o3/commit.hh Tue Jan 18 16:30:05 2011 -0600
+++ b/src/cpu/o3/commit.hh Tue Jan 18 16:30:05 2011 -0600
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -409,6 +421,9 @@
/** The sequence number of the youngest valid instruction in the ROB. */
InstSeqNum youngestSeqNum[Impl::MaxThreads];
+ /** The sequence number of the last commited instruction. */
+ InstSeqNum lastCommitedSeqNum[Impl::MaxThreads];
+
/** Records if there is a trap currently in flight. */
bool trapInFlight[Impl::MaxThreads];
diff -r 3c6783497976 -r c0be563517da src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Tue Jan 18 16:30:05 2011 -0600
+++ b/src/cpu/o3/commit_impl.hh Tue Jan 18 16:30:05 2011 -0600
@@ -141,6 +141,7 @@
trapSquash[tid] = false;
tcSquash[tid] = false;
pc[tid].set(0);
+ lastCommitedSeqNum[tid] = 0;
}
#if FULL_SYSTEM
interrupt = NoFault;
@@ -498,12 +499,12 @@
// Hopefully this doesn't mess things up. Basically I want to squash
// all instructions of this thread.
InstSeqNum squashed_inst = rob->isEmpty() ?
- 0 : rob->readHeadInst(tid)->seqNum - 1;
+ lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
// All younger instructions will be squashed. Set the sequence
// number as the youngest instruction in the ROB (0 in this case.
// Hopefully nothing breaks.)
- youngestSeqNum[tid] = 0;
+ youngestSeqNum[tid] = lastCommitedSeqNum[tid];
rob->squash(squashed_inst, tid);
changedROBNumEntries[tid] = true;
@@ -960,6 +961,9 @@
TheISA::advancePC(pc[tid], head_inst->staticInst);
+ // Keep track of the last sequence number commited
+ lastCommitedSeqNum[tid] = head_inst->seqNum;
+
// If this is an instruction that doesn't play nicely with
// others squash everything and restart fetch
if (head_inst->isSquashAfter())
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