changeset 535cc70e8663 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=535cc70e8663
description:
Stats: Update stats for previous set of patches.
diffstat:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout |
6 +-
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt |
11 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout |
10 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt |
519 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout |
8 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt |
1862 +++++-----
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout |
8 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt |
936 ++--
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout |
6 +-
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt |
11 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout |
6 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt |
13 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout |
6 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt |
11 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout |
6 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt |
11 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout |
6 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt |
11 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/simout |
6 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt |
11 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout |
6 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt |
9 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/simout |
6 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt |
9 +-
tests/quick/00.hello/ref/power/linux/o3-timing/simerr |
2 +-
tests/quick/00.hello/ref/power/linux/o3-timing/simout |
6 +-
tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt |
11 +-
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout |
6 +-
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt |
11 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout |
8 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt |
11 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini |
4 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr |
6 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout |
14 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt |
488 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status |
2 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout |
8 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt |
20 +-
38 files changed, 2057 insertions(+), 2034 deletions(-)
diffs (truncated from 5686 to 300 lines):
diff -r ee6641d7c713 -r 535cc70e8663
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Tue Jan 18
16:30:05 2011 -0600
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Tue Jan 18
16:30:06 2011 -0600
@@ -5,9 +5,9 @@
All Rights Reserved
-M5 compiled Nov 15 2010 08:52:32
-M5 revision f440cdaf1c2d+ 7743+ default tip
-M5 started Nov 15 2010 08:53:40
+M5 compiled Jan 17 2011 16:24:53
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 16:40:29
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff -r ee6641d7c713 -r 535cc70e8663
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Tue Jan 18
16:30:05 2011 -0600
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Tue Jan 18
16:30:06 2011 -0600
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 195051 #
Simulator instruction rate (inst/s)
-host_mem_usage 206584 #
Number of bytes of host memory used
-host_seconds 2899.51 #
Real time elapsed on the host
-host_tick_rate 56140502 #
Simulator tick rate (ticks/s)
+host_inst_rate 207877 #
Simulator instruction rate (inst/s)
+host_mem_usage 206352 #
Number of bytes of host memory used
+host_seconds 2720.61 #
Real time elapsed on the host
+host_tick_rate 59832123 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 565552443 #
Number of instructions simulated
sim_seconds 0.162780 #
Number of seconds simulated
@@ -145,9 +145,10 @@
system.cpu.dtb.write_misses 27547 #
DTB write misses
system.cpu.fetch.Branches 76295210 #
Number of branches that fetch encountered
system.cpu.fetch.CacheLines 65560315 #
Number of cache lines fetched
-system.cpu.fetch.Cycles 195638983 #
Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles 130078631 #
Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1304986 #
Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 697895611 #
Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 37 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
system.cpu.fetch.SquashCycles 4169829 #
Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.234351 #
Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 65560315 #
Number of cycles fetch is stalled on an Icache miss
diff -r ee6641d7c713 -r 535cc70e8663
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout Tue Jan 18
16:30:05 2011 -0600
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout Tue Jan 18
16:30:06 2011 -0600
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled Jan 15 2011 04:38:18
-M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip
-M5 started Jan 15 2011 04:38:23
-M5 executing on tater
+M5 compiled Jan 17 2011 21:17:52
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 21:17:55
+M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d
build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py
build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -43,4 +43,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 601459117000 because target called exit()
+Exiting @ tick 601458924000 because target called exit()
diff -r ee6641d7c713 -r 535cc70e8663
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt Tue Jan 18
16:30:05 2011 -0600
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt Tue Jan 18
16:30:06 2011 -0600
@@ -1,63 +1,63 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 115319 #
Simulator instruction rate (inst/s)
-host_mem_usage 220936 #
Number of bytes of host memory used
-host_seconds 12188.85 #
Real time elapsed on the host
-host_tick_rate 49345009 #
Simulator tick rate (ticks/s)
+host_inst_rate 144426 #
Simulator instruction rate (inst/s)
+host_mem_usage 207996 #
Number of bytes of host memory used
+host_seconds 9732.45 #
Real time elapsed on the host
+host_tick_rate 61799305 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 1405604152 #
Number of instructions simulated
sim_seconds 0.601459 #
Number of seconds simulated
-sim_ticks 601459117000 #
Number of ticks simulated
+sim_ticks 601458924000 #
Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 98804472 #
Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 100538302 #
Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 98804590 #
Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 100538418 #
Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 #
Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 5348297 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 105813027 #
Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 105813027 #
Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 5348296 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 105813144 #
Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 105813144 #
Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 #
Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 86248929 #
Number of branches committed
-system.cpu.commit.COM:bw_lim_events 21327805 #
number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 21328117 #
number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 1172142381
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 1172142071
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.270770
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.680117
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 418030405 35.66%
35.66% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 498323124 42.51%
78.18% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 52996988 4.52%
82.70% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 103673812 8.84%
91.54% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 32915552 2.81%
94.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 8294276 0.71%
95.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 25634202 2.19%
97.25% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 10946217 0.93%
98.18% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 21327805 1.82%
100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 418029830 35.66%
35.66% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 498322942 42.51%
78.18% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 52997650 4.52%
82.70% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 103674512 8.84%
91.54% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 32914783 2.81%
94.35% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 8294110 0.71%
95.06% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 25633990 2.19%
97.25% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 10946137 0.93%
98.18% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 21328117 1.82%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 1172142381
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 1172142071
# Number of insts commited each cycle
system.cpu.commit.COM:count 1489523295 #
Number of instructions committed
system.cpu.commit.COM:loads 402512844 #
Number of loads committed
system.cpu.commit.COM:membars 51356 #
Number of memory barriers committed
system.cpu.commit.COM:refs 569360986 #
Number of memory references committed
system.cpu.commit.COM:swp_count 0 #
Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 5348297 #
The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 5348296 #
The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489523295 #
The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243671 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 219358890 #
The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 219357232 #
The number of squashed insts skipped by commit
system.cpu.committedInsts 1405604152 #
Number of Instructions Simulated
system.cpu.committedInsts_total 1405604152 #
Number of Instructions Simulated
-system.cpu.cpi 0.855802 #
CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.855802 #
CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 295702052 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14658.314544
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.427114
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 294883757 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 11994825500 #
number of ReadReq miss cycles
+system.cpu.cpi 0.855801 #
CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.855801 #
CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 295701881 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14657.940821
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.771391
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 294883584 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 11994549000 #
number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002767 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 818295 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 604804 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1593801500
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses 818297 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 604806 #
number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1593875000
# number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000722 #
mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 213491 #
number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 #
number of SwapReq accesses(hits+misses)
@@ -71,50 +71,50 @@
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 #
mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 7 #
number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166846816 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 15552.195709
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.845351
# average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 165080578 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 27468879045 #
number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.010586 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1766238 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1498173 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 3438428299
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 15553.543798
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12825.966833
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 165080859 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 27466889545 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.010584 #
miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1765957 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1497892 #
number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 3438192799
# number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 #
mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 268065 #
number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 955.151567 #
Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 955.151791 #
Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 462548868 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 15269.181916 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 10449.936869
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 459964335 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 39463704545 #
number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.005588 #
miss rate for demand accesses
-system.cpu.dcache.demand_misses 2584533 #
number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2102977 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5032229799
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_accesses 462548697 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 15269.953551 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 10449.600460
# average overall mshr miss latency
+system.cpu.dcache.demand_hits 459964443 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 39461438545 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.005587 #
miss rate for demand accesses
+system.cpu.dcache.demand_misses 2584254 #
number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2102698 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 5032067799
# number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.001041 #
mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 481556 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999859 #
Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4095.424477 #
Average occupied blocks per context
-system.cpu.dcache.overall_accesses 462548868 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 15269.181916
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 10449.936869
# average overall mshr miss latency
+system.cpu.dcache.occ_blocks::0 4095.424247 #
Average occupied blocks per context
+system.cpu.dcache.overall_accesses 462548697 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 15269.953551
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 10449.600460
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 459964335 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 39463704545 #
number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.005588 #
miss rate for overall accesses
-system.cpu.dcache.overall_misses 2584533 #
number of overall misses
-system.cpu.dcache.overall_mshr_hits 2102977 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5032229799
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_hits 459964443 #
number of overall hits
+system.cpu.dcache.overall_miss_latency 39461438545 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.005587 #
miss rate for overall accesses
+system.cpu.dcache.overall_misses 2584254 #
number of overall misses
+system.cpu.dcache.overall_mshr_hits 2102698 #
number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 5032067799
# number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.001041 #
mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 481556 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
@@ -122,129 +122,130 @@
system.cpu.dcache.replacements 477467 #
number of replacements
system.cpu.dcache.sampled_refs 481563 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.424477 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 459965654 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 132267000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.tagsinuse 4095.424247 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 459965762 #
Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 132304000 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 428418 #
number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 393632591 #
Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 1750743071 #
Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 405697785 #
Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 351108006 #
Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 30410701 #
Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 21703388 #
Number of cycles decode is unblocking
-system.cpu.fetch.Branches 105813027 #
Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 173096803 #
Number of cache lines fetched
-system.cpu.fetch.Cycles 548235394 #
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 1429408 #
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 1755979705 #
Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 6170644 #
Number of cycles fetch has spent squashing
+system.cpu.decode.DECODE:BlockedCycles 393633604 #
Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 1750740297 #
Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 405697462 #
Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 351107020 #
Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 30410517 #
Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 21703374 #
Number of cycles decode is unblocking
+system.cpu.fetch.Branches 105813144 #
Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 173097327 #
Number of cache lines fetched
+system.cpu.fetch.Cycles 375137003 #
Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1429156 #
Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 1755978912 #
Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 47 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
+system.cpu.fetch.SquashCycles 6170643 #
Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.087964 #
Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 173096803 #
Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 98804472 #
Number of branches that fetch has predicted taken
+system.cpu.fetch.icacheStallCycles 173097327 #
Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 98804590 #
Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.459766 #
Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 1202552471 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.464003 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 1202551977 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.463999 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.699994 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 827413927 68.80% 68.80% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 82887157 6.89% 75.70% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 45822503 3.81% 79.51% #
Number of instructions fetched each cycle (Total)
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