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I still don't understand how the CPU ends up in a bad state. Could you please list step by step how it happens? Use little words and go slowly :-). - Gabe On 2011-01-18 14:34:11, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/431/ > ----------------------------------------------------------- > > (Updated 2011-01-18 14:34:11) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk > occurs. > > This change fixes an issue where a DTLB fault occurs and redirects fetch to > handle the fault and the ITLB requires a walk which delays translation. In > this > case the status of the cpu isn't updated appropriately, and an additional > instruction fetch occurs. Eventually this hits an assert as multiple > instruction > fetches are occuring in the system and when the second one returns the > processor is in the wrong state. > > Some asserts below are removed because it was always true (typo) and the state > after the initiateAcc() the processor could be in any valid state when a > d-side fault occurs. > > > Diffs > ----- > > src/cpu/simple/timing.hh 32b6354d2ae6 > src/cpu/simple/timing.cc 32b6354d2ae6 > > Diff: http://reviews.m5sim.org/r/431/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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