----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/444/ -----------------------------------------------------------
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- inorder: stage width as a python parameter ==== This change makes superscalar InOrder CPU functional in M5 ==== allow the user to specify how many instructions a pipeline stage can process on any given cycle (stageWidth...i.e.bandwidth) by setting the parameter through the python interface rather than compile the code after changing the *.cc file. (we always had the parameter there, but still used the static 'ThePipeline::StageWidth' instead) - Since StageWidth is now dynamically defined, change the interstage communication structure to use a vector and get rid of array and array handling index (toNextStageIndex) since we can just make calls to the list for the same information Diffs ----- src/cpu/inorder/InOrderCPU.py 31a04e5ac4be src/cpu/inorder/comm.hh 31a04e5ac4be src/cpu/inorder/cpu.hh 31a04e5ac4be src/cpu/inorder/cpu.cc 31a04e5ac4be src/cpu/inorder/pipeline_stage.cc 31a04e5ac4be src/cpu/inorder/pipeline_traits.hh 31a04e5ac4be src/cpu/inorder/resource_pool.cc 31a04e5ac4be Diff: http://reviews.m5sim.org/r/444/diff Testing ------- Thanks, Korey
_______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
