----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/422/#review756 -----------------------------------------------------------
Any further comments on this? It doesn't alter the regressions at all, so I would like to commit it, even if we change initiateAcc() to not return a fault in the future. Ali src/cpu/simple/timing.hh <http://reviews.m5sim.org/r/422/#comment1019> I'm pretty sure I'm going to use this for my dtlb followed by itlb walk issue in the timing simple cpu. src/cpu/translation.hh <http://reviews.m5sim.org/r/422/#comment1021> It's used right here. src/sim/tlb.hh <http://reviews.m5sim.org/r/422/#comment1018> All the regressions still pass... This isn't the base tlb object, it's the translation object so yes, it's been added to all the cpu models. - Ali On 2011-01-12 09:12:18, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/422/ > ----------------------------------------------------------- > > (Updated 2011-01-12 09:12:18) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Enhance data address translation by supporting hardware page table > walkers. > > Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, > when a TLB miss occurs, initiateTranslation() can return with NoFault but with > the translation unfinished. > > Instructions experiencing a delayed translation due to a hardware page table > walk are deferred until the translation completes and kept into the IQ. In > order to keep track of them, the IQ has been augmented with a queue of the > outstanding delayed memory instructions. When their translation completes, > instructions are re-executed (only their initiateAccess() was already > executed; their DTB translation is now skipped). The IEW stage has been > modified to support such a 2-pass execution. > > > Diffs > ----- > > src/arch/arm/tlb.cc 5d0f62927d75 > src/cpu/base_dyn_inst.hh 5d0f62927d75 > src/cpu/base_dyn_inst_impl.hh 5d0f62927d75 > src/cpu/o3/fetch.hh 5d0f62927d75 > src/cpu/o3/iew_impl.hh 5d0f62927d75 > src/cpu/o3/inst_queue.hh 5d0f62927d75 > src/cpu/o3/inst_queue_impl.hh 5d0f62927d75 > src/cpu/o3/lsq_unit_impl.hh 5d0f62927d75 > src/cpu/simple/timing.hh 5d0f62927d75 > src/cpu/translation.hh 5d0f62927d75 > src/sim/tlb.hh 5d0f62927d75 > > Diff: http://reviews.m5sim.org/r/422/diff > > > Testing > ------- > > > Thanks, > > Ali > >
_______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
