----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/438/ -----------------------------------------------------------
Review request for Default. Summary ------- The patch changes the order in which L1 dcache and icache are looked up when a request comes in. Earlier, if a request came in for instruction fetch, the dcache was looked up before the icache, to correctly handle self-modifying code. But, in the common case, dcache is going to report a miss and the subsequent icache lookup is going to report a hit. Given the invariant - caches under the same controller keep track of disjoint sets of cache blocks, we can move the icache lookup before the dcache lookup. In case of a hit in the icache, using our invariant, we know that the dcache would have reported a miss. In case of a miss in the icache, we know that icache would have missed even if the dcache was looked up before looking up the icache. Effectively, we are doing the same thing as before, though in the common case, we expect reduction in the number of lookups. This was empirically confirmed for MOESI hammer. The ratio lookups to access requests is now about 1.1 to 1. Diffs ----- src/mem/protocol/MESI_CMP_directory-L1cache.sm 31a04e5ac4be src/mem/protocol/MOESI_CMP_directory-L1cache.sm 31a04e5ac4be src/mem/protocol/MOESI_CMP_token-L1cache.sm 31a04e5ac4be src/mem/protocol/MOESI_hammer-cache.sm 31a04e5ac4be Diff: http://reviews.m5sim.org/r/438/diff Testing ------- All the protocols have been tested using ruby random tester. The parameters supplied were l = 10000, n = 4. MOESI hammer was profiled using ruby_fs.py. Thanks, Nilay
_______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
