changeset 303293e1517f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=303293e1517f
description:
inorder: implement separate fetch unit
instead of having one cache-unit class be responsible for both data and
code
accesses, separate code that is just for fetch in it's own derived
class off the
original base class. This makes the code easier to manage as well as
handle
future cases of special fetch handling
diffstat:
src/cpu/inorder/SConscript | 1 +
src/cpu/inorder/pipeline_traits.cc | 4 +-
src/cpu/inorder/resource_pool.cc | 2 +-
src/cpu/inorder/resources/cache_unit.cc | 101 +--------
src/cpu/inorder/resources/cache_unit.hh | 41 +--
src/cpu/inorder/resources/fetch_unit.cc | 333 +++++++++++++++++++++++++++++
src/cpu/inorder/resources/fetch_unit.hh | 107 +++++++++
src/cpu/inorder/resources/resource_list.hh | 1 +
8 files changed, 456 insertions(+), 134 deletions(-)
diffs (truncated from 722 to 300 lines):
diff -r 6e810a479c3e -r 303293e1517f src/cpu/inorder/SConscript
--- a/src/cpu/inorder/SConscript Fri Feb 04 00:08:19 2011 -0500
+++ b/src/cpu/inorder/SConscript Fri Feb 04 00:08:20 2011 -0500
@@ -75,6 +75,7 @@
Source('resources/bpred_unit.cc')
Source('resources/branch_predictor.cc')
Source('resources/cache_unit.cc')
+ Source('resources/fetch_unit.cc')
Source('resources/use_def.cc')
Source('resources/decode_unit.cc')
Source('resources/inst_buffer.cc')
diff -r 6e810a479c3e -r 303293e1517f src/cpu/inorder/pipeline_traits.cc
--- a/src/cpu/inorder/pipeline_traits.cc Fri Feb 04 00:08:19 2011 -0500
+++ b/src/cpu/inorder/pipeline_traits.cc Fri Feb 04 00:08:20 2011 -0500
@@ -70,10 +70,10 @@
// FETCH
F->needs(FetchSeq, FetchSeqUnit::AssignNextPC);
- F->needs(ICache, CacheUnit::InitiateFetch);
+ F->needs(ICache, FetchUnit::InitiateFetch);
// DECODE
- D->needs(ICache, CacheUnit::CompleteFetch);
+ D->needs(ICache, FetchUnit::CompleteFetch);
D->needs(Decode, DecodeUnit::DecodeInst);
D->needs(BPred, BranchPredictor::PredictBranch);
D->needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
diff -r 6e810a479c3e -r 303293e1517f src/cpu/inorder/resource_pool.cc
--- a/src/cpu/inorder/resource_pool.cc Fri Feb 04 00:08:19 2011 -0500
+++ b/src/cpu/inorder/resource_pool.cc Fri Feb 04 00:08:20 2011 -0500
@@ -54,7 +54,7 @@
stage_width * 2, 0, _cpu, params));
memObjects.push_back(ICache);
- resources.push_back(new CacheUnit("icache_port", ICache,
+ resources.push_back(new FetchUnit("icache_port", ICache,
stage_width * MaxThreads, 0, _cpu,
params));
diff -r 6e810a479c3e -r 303293e1517f src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Fri Feb 04 00:08:19 2011 -0500
+++ b/src/cpu/inorder/resources/cache_unit.cc Fri Feb 04 00:08:20 2011 -0500
@@ -335,14 +335,6 @@
inst->readTid(), inst->seqNum, inst->getMemAddr());
break;
- case InitiateFetch:
- pkt_cmd = MemCmd::ReadReq;
-
- DPRINTF(InOrderCachePort,
- "[tid:%i]: Fetch request from [sn:%i] for addr %08p\n",
- inst->readTid(), inst->seqNum, inst->getMemAddr());
- break;
-
default:
panic("%i: Unexpected request type (%i) to %s", curTick(),
sched_entry->cmd, name());
@@ -672,38 +664,13 @@
DynInstPtr inst = cache_req->inst;
#if TRACING_ON
ThreadID tid = inst->readTid();
- int seq_num = inst->seqNum;
std::string acc_type = "write";
-
#endif
cache_req->fault = NoFault;
switch (cache_req->cmd)
{
- case InitiateFetch:
- {
- //@TODO: Switch to size of full cache block. Store in fetch buffer
- int acc_size = sizeof(TheISA::MachInst);
-
- doTLBAccess(inst, cache_req, acc_size, 0, TheISA::TLB::Execute);
-
- // Only Do Access if no fault from TLB
- if (cache_req->fault == NoFault) {
-
- DPRINTF(InOrderCachePort,
- "[tid:%u]: Initiating fetch access to %s for addr. %08p\n",
- tid, name(), cache_req->inst->getMemAddr());
-
- cache_req->reqData = new uint8_t[acc_size];
-
- inst->setCurResSlot(slot_num);
-
- doCacheAccess(inst);
- }
-
- break;
- }
case InitiateReadData:
#if TRACING_ON
@@ -749,39 +716,6 @@
inst->split2ndAddr, inst->split2ndFlags, NULL);
break;
-
- case CompleteFetch:
- if (cache_req->isMemAccComplete()) {
- DPRINTF(InOrderCachePort,
- "[tid:%i]: Completing Fetch Access for [sn:%i]\n",
- tid, inst->seqNum);
-
-
- DPRINTF(InOrderCachePort, "[tid:%i]: Instruction [sn:%i] is: %s\n",
- tid, seq_num,
- inst->staticInst->disassemble(inst->instAddr()));
-
- removeAddrDependency(inst);
-
- delete cache_req->dataPkt;
-
- // Do not stall and switch threads for fetch... for now..
- // TODO: We need to detect cache misses for latencies > 1
- // cache_req->setMemStall(false);
-
- cache_req->done();
- } else {
- DPRINTF(InOrderCachePort,
- "[tid:%i]: [sn:%i]: Unable to Complete Fetch Access\n",
- tid, inst->seqNum);
- DPRINTF(InOrderStall,
- "STALL: [tid:%i]: Fetch miss from %08p\n",
- tid, cache_req->inst->instAddr());
- cache_req->setCompleted(false);
- //cache_req->setMemStall(true);
- }
- break;
-
case CompleteReadData:
case CompleteWriteData:
DPRINTF(InOrderCachePort,
@@ -999,40 +933,7 @@
ThreadID tid = cache_req->inst->readTid();
if (!cache_req->isSquashed()) {
- if (inst->resSched.top()->cmd == CompleteFetch) {
- DPRINTF(InOrderCachePort,
- "[tid:%u]: [sn:%i]: Processing fetch access\n",
- tid, inst->seqNum);
-
- // NOTE: This is only allowing a thread to fetch one line
- // at a time. Re-examine when/if prefetching
- // gets implemented.
- //memcpy(fetchData[tid], cache_pkt->getPtr<uint8_t>(),
- // cache_pkt->getSize());
-
- // Get the instruction from the array of the cache line.
- // @todo: update thsi
- ExtMachInst ext_inst;
- StaticInstPtr staticInst = NULL;
- TheISA::PCState instPC = inst->pcState();
- MachInst mach_inst =
- TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
- (cache_pkt->getPtr<uint8_t>()));
-
- predecoder.setTC(cpu->thread[tid]->getTC());
- predecoder.moreBytes(instPC, inst->instAddr(), mach_inst);
- ext_inst = predecoder.getExtMachInst(instPC);
- inst->pcState(instPC);
-
- inst->setMachInst(ext_inst);
-
- // Set Up More TraceData info
- if (inst->traceData) {
- inst->traceData->setStaticInst(inst->staticInst);
- inst->traceData->setPC(instPC);
- }
-
- } else if (inst->staticInst && inst->isMemRef()) {
+ if (inst->staticInst && inst->isMemRef()) {
DPRINTF(InOrderCachePort,
"[tid:%u]: [sn:%i]: Processing cache access\n",
tid, inst->seqNum);
diff -r 6e810a479c3e -r 303293e1517f src/cpu/inorder/resources/cache_unit.hh
--- a/src/cpu/inorder/resources/cache_unit.hh Fri Feb 04 00:08:19 2011 -0500
+++ b/src/cpu/inorder/resources/cache_unit.hh Fri Feb 04 00:08:20 2011 -0500
@@ -64,15 +64,10 @@
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
enum Command {
- InitiateFetch,
- CompleteFetch,
InitiateReadData,
CompleteReadData,
InitiateWriteData,
CompleteWriteData,
- Fetch,
- ReadData,
- WriteData,
InitSecondSplitRead,
InitSecondSplitWrite,
CompleteSecondSplitRead,
@@ -125,39 +120,32 @@
void init();
ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
- int res_idx, int slot_num,
- unsigned cmd);
+ int res_idx, int slot_num,
+ unsigned cmd);
ResReqPtr findRequest(DynInstPtr inst);
ResReqPtr findSplitRequest(DynInstPtr inst, int idx);
void requestAgain(DynInstPtr inst, bool &try_request);
- int getSlot(DynInstPtr inst);
+ virtual int getSlot(DynInstPtr inst);
- /** Execute the function of this resource. The Default is action
- * is to do nothing. More specific models will derive from this
- * class and define their own execute function.
- */
- void execute(int slot_num);
+ /** Executes one of the commands from the "Command" enum */
+ virtual void execute(int slot_num);
- void squash(DynInstPtr inst, int stage_num,
+ virtual void squash(DynInstPtr inst, int stage_num,
InstSeqNum squash_seq_num, ThreadID tid);
void squashDueToMemStall(DynInstPtr inst, int stage_num,
InstSeqNum squash_seq_num, ThreadID tid);
- /** Processes cache completion event. */
- void processCacheCompletion(PacketPtr pkt);
+ /** After memory request is completedd in the cache, then do final
+ processing to complete the request in the CPU.
+ */
+ virtual void processCacheCompletion(PacketPtr pkt);
void recvRetry();
- /** Align a PC to the start of an I-cache block. */
- Addr cacheBlockAlignPC(Addr addr)
- {
- return (addr & ~(cacheBlkMask));
- }
-
/** Returns a specific port. */
Port *getPort(const std::string &if_name, int idx);
@@ -202,15 +190,6 @@
return (addr & ~(cacheBlkMask));
}
- /** The mem line being fetched. */
- uint8_t *fetchData[ThePipeline::MaxThreads];
-
- /** @TODO: Move functionaly of fetching more than
- one instruction to 'fetch unit'*/
- /** The Addr of the cacheline that has been loaded. */
- //Addr cacheBlockAddr[ThePipeline::MaxThreads];
- //unsigned fetchOffset[ThePipeline::MaxThreads];
-
TheISA::Predecoder predecoder;
bool tlbBlocked[ThePipeline::MaxThreads];
diff -r 6e810a479c3e -r 303293e1517f src/cpu/inorder/resources/fetch_unit.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/cpu/inorder/resources/fetch_unit.cc Fri Feb 04 00:08:20 2011 -0500
@@ -0,0 +1,333 @@
+/*
+ * Copyright (c) 2011 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
+ *
+ */
+
+#include <vector>
+#include <list>
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