changeset 6fa135943891 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6fa135943891
description:
inorder: fault handling
Maintain all information about an instruction's fault in the DynInst
object rather
than any cpu-request object. Also, if there is a fault during the
execution stage
then just save the fault inside the instruction and trap once the
instruction
tries to graduate
diffstat:
src/cpu/inorder/pipeline_stage.cc | 7 +------
src/cpu/inorder/resource.cc | 1 -
src/cpu/inorder/resource.hh | 3 ---
src/cpu/inorder/resources/agen_unit.cc | 9 +++------
src/cpu/inorder/resources/branch_predictor.cc | 4 ----
src/cpu/inorder/resources/cache_unit.cc | 24 +++++++++++-------------
src/cpu/inorder/resources/cache_unit.hh | 4 ++--
src/cpu/inorder/resources/decode_unit.cc | 3 ---
src/cpu/inorder/resources/execution_unit.cc | 20 ++++++++------------
src/cpu/inorder/resources/fetch_seq_unit.cc | 2 --
src/cpu/inorder/resources/fetch_unit.cc | 5 +++--
src/cpu/inorder/resources/graduation_unit.cc | 25 +++++++------------------
src/cpu/inorder/resources/inst_buffer.cc | 2 --
src/cpu/inorder/resources/mult_div_unit.cc | 17 +++++------------
14 files changed, 40 insertions(+), 86 deletions(-)
diffs (truncated from 434 to 300 lines):
diff -r 1ffb11f8e8bb -r 6fa135943891 src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Fri Feb 04 00:09:19 2011 -0500
+++ b/src/cpu/inorder/pipeline_stage.cc Fri Feb 04 00:09:20 2011 -0500
@@ -944,12 +944,7 @@
"completed.\n", tid, inst->seqNum,
cpu->resPool->name(res_num));
- if (req->fault == NoFault) {
- inst->popSchedEntry();
- } else {
- panic("%i: encountered %s fault!\n",
- curTick(), req->fault->name());
- }
+ inst->popSchedEntry();
reqs_processed++;
diff -r 1ffb11f8e8bb -r 6fa135943891 src/cpu/inorder/resource.cc
--- a/src/cpu/inorder/resource.cc Fri Feb 04 00:09:19 2011 -0500
+++ b/src/cpu/inorder/resource.cc Fri Feb 04 00:09:20 2011 -0500
@@ -277,7 +277,6 @@
DPRINTF(Resource, "[tid:%i]: Executing %s resource.\n",
reqMap[slot_idx]->getTid(), name());
reqMap[slot_idx]->setCompleted(true);
- reqMap[slot_idx]->fault = NoFault;
reqMap[slot_idx]->done();
}
diff -r 1ffb11f8e8bb -r 6fa135943891 src/cpu/inorder/resource.hh
--- a/src/cpu/inorder/resource.hh Fri Feb 04 00:09:19 2011 -0500
+++ b/src/cpu/inorder/resource.hh Fri Feb 04 00:09:20 2011 -0500
@@ -350,9 +350,6 @@
/** Not guaranteed to be set, used for debugging */
InstSeqNum seqNum;
- /** Fault Associated With This Resource Request */
- Fault fault;
-
/** Command For This Resource */
unsigned cmd;
diff -r 1ffb11f8e8bb -r 6fa135943891 src/cpu/inorder/resources/agen_unit.cc
--- a/src/cpu/inorder/resources/agen_unit.cc Fri Feb 04 00:09:19 2011 -0500
+++ b/src/cpu/inorder/resources/agen_unit.cc Fri Feb 04 00:09:20 2011 -0500
@@ -52,14 +52,11 @@
{
ResourceRequest* agen_req = reqMap[slot_num];
DynInstPtr inst = reqMap[slot_num]->inst;
- Fault fault = reqMap[slot_num]->fault;
#if TRACING_ON
ThreadID tid = inst->readTid();
#endif
int seq_num = inst->seqNum;
- agen_req->fault = NoFault;
-
switch (agen_req->cmd)
{
case GenerateAddr:
@@ -70,18 +67,18 @@
"[tid:%i] Generating Address for [sn:%i] (%s).\n",
tid, seq_num, inst->staticInst->getName());
- fault = inst->calcEA();
+ inst->fault = inst->calcEA();
inst->setMemAddr(inst->getEA());
DPRINTF(InOrderAGEN,
"[tid:%i] [sn:%i] Effective address calculated as: %#x\n",
tid, seq_num, inst->getEA());
- if (fault == NoFault) {
+ if (inst->fault == NoFault) {
agen_req->done();
} else {
fatal("%s encountered while calculating address [sn:%i]",
- fault->name(), seq_num);
+ inst->fault->name(), seq_num);
}
agens++;
diff -r 1ffb11f8e8bb -r 6fa135943891
src/cpu/inorder/resources/branch_predictor.cc
--- a/src/cpu/inorder/resources/branch_predictor.cc Fri Feb 04 00:09:19
2011 -0500
+++ b/src/cpu/inorder/resources/branch_predictor.cc Fri Feb 04 00:09:20
2011 -0500
@@ -67,13 +67,9 @@
// After this is working, change this to a reinterpret cast
// for performance considerations
ResourceRequest* bpred_req = reqMap[slot_num];
-
DynInstPtr inst = bpred_req->inst;
ThreadID tid = inst->readTid();
int seq_num = inst->seqNum;
- //int stage_num = bpred_req->getStageNum();
-
- bpred_req->fault = NoFault;
switch (bpred_req->cmd)
{
diff -r 1ffb11f8e8bb -r 6fa135943891 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Fri Feb 04 00:09:19 2011 -0500
+++ b/src/cpu/inorder/resources/cache_unit.cc Fri Feb 04 00:09:20 2011 -0500
@@ -405,7 +405,7 @@
}
}
-Fault
+void
CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
int flags, TheISA::TLB::Mode tlb_mode)
{
@@ -416,13 +416,13 @@
setupMemRequest(inst, cache_req, acc_size, flags);
- cache_req->fault =
+ inst->fault =
_tlb->translateAtomic(cache_req->memReq,
cpu->thread[tid]->getTC(), tlb_mode);
- if (cache_req->fault != NoFault) {
+ if (inst->fault != NoFault) {
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
- "addr:%08p for [sn:%i].\n", tid, cache_req->fault->name(),
+ "addr:%08p for [sn:%i].\n", tid, inst->fault->name(),
cache_req->memReq->getVaddr(), inst->seqNum);
cpu->pipelineStage[stage_num]->setResStall(cache_req, tid);
@@ -433,7 +433,7 @@
scheduleEvent(slot_idx, 1);
- cpu->trap(cache_req->fault, tid, inst);
+ cpu->trap(inst->fault, tid, inst);
} else {
DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
"to phys. addr:%08p.\n", tid, inst->seqNum,
@@ -441,7 +441,6 @@
cache_req->memReq->getPaddr());
}
- return cache_req->fault;
}
Fault
@@ -531,7 +530,7 @@
doTLBAccess(inst, cache_req, size, flags, TheISA::TLB::Read);
- if (cache_req->fault == NoFault) {
+ if (inst->fault == NoFault) {
if (!cache_req->splitAccess) {
cache_req->reqData = new uint8_t[size];
doCacheAccess(inst, NULL);
@@ -546,7 +545,7 @@
}
}
- return cache_req->fault;
+ return inst->fault;
}
Fault
@@ -638,7 +637,7 @@
doTLBAccess(inst, cache_req, size, flags, TheISA::TLB::Write);
- if (cache_req->fault == NoFault) {
+ if (inst->fault == NoFault) {
if (!cache_req->splitAccess) {
// Remove this line since storeData is saved in INST?
cache_req->reqData = new uint8_t[size];
@@ -649,7 +648,7 @@
}
- return cache_req->fault;
+ return inst->fault;
}
@@ -672,7 +671,7 @@
std::string acc_type = "write";
#endif
- cache_req->fault = NoFault;
+ inst->fault = NoFault;
switch (cache_req->cmd)
{
@@ -785,7 +784,7 @@
}
// @TODO: Split into doCacheRead() and doCacheWrite()
-Fault
+void
CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res,
CacheReqPtr split_req)
{
@@ -883,7 +882,6 @@
cache_req->setCompleted(false);
}
- return fault;
}
void
diff -r 1ffb11f8e8bb -r 6fa135943891 src/cpu/inorder/resources/cache_unit.hh
--- a/src/cpu/inorder/resources/cache_unit.hh Fri Feb 04 00:09:19 2011 -0500
+++ b/src/cpu/inorder/resources/cache_unit.hh Fri Feb 04 00:09:20 2011 -0500
@@ -161,13 +161,13 @@
Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
- Fault doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
+ void doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
int flags, TheISA::TLB::Mode tlb_mode);
/** Read/Write on behalf of an instruction.
* curResSlot needs to be a valid value in instruction.
*/
- Fault doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL,
+ void doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL,
CacheReqPtr split_req=NULL);
uint64_t getMemData(Packet *packet);
diff -r 1ffb11f8e8bb -r 6fa135943891 src/cpu/inorder/resources/decode_unit.cc
--- a/src/cpu/inorder/resources/decode_unit.cc Fri Feb 04 00:09:19 2011 -0500
+++ b/src/cpu/inorder/resources/decode_unit.cc Fri Feb 04 00:09:20 2011 -0500
@@ -51,11 +51,8 @@
{
ResourceRequest* decode_req = reqMap[slot_num];
DynInstPtr inst = reqMap[slot_num]->inst;
- Fault fault = reqMap[slot_num]->fault;
ThreadID tid = inst->readTid();
- decode_req->fault = NoFault;
-
switch (decode_req->cmd)
{
case DecodeInst:
diff -r 1ffb11f8e8bb -r 6fa135943891 src/cpu/inorder/resources/execution_unit.cc
--- a/src/cpu/inorder/resources/execution_unit.cc Fri Feb 04 00:09:19
2011 -0500
+++ b/src/cpu/inorder/resources/execution_unit.cc Fri Feb 04 00:09:20
2011 -0500
@@ -84,14 +84,11 @@
{
ResourceRequest* exec_req = reqMap[slot_num];
DynInstPtr inst = reqMap[slot_num]->inst;
- Fault fault = reqMap[slot_num]->fault;
- ThreadID tid = inst->readTid();
+ Fault fault = NoFault;
int seq_num = inst->seqNum;
- exec_req->fault = NoFault;
-
DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
- tid, seq_num, inst->pcState(), inst->instName());
+ inst->readTid(), seq_num, inst->pcState(), inst->instName());
switch (exec_req->cmd)
{
@@ -126,7 +123,6 @@
if (inst->mispredicted()) {
int stage_num = exec_req->getStageNum();
ThreadID tid = inst->readTid();
-
// If it's a branch ...
if (inst->isDirectCtrl()) {
assert(!inst->isIndirectCtrl());
@@ -247,13 +243,13 @@
seq_num,
(inst->resultType(0) == InOrderDynInst::Float) ?
inst->readFloatResult(0) : inst->readIntResult(0));
+ } else {
+ DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
+ "fault.\n", inst->readTid(), seq_num,
fault->name());
+ inst->fault = fault;
+ }
- exec_req->done();
- } else {
- warn("inst [sn:%i] had a %s fault",
- seq_num, fault->name());
- cpu->trap(fault, tid, inst);
- }
+ exec_req->done();
}
}
break;
diff -r 1ffb11f8e8bb -r 6fa135943891 src/cpu/inorder/resources/fetch_seq_unit.cc
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc Fri Feb 04 00:09:19
2011 -0500
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc Fri Feb 04 00:09:20
2011 -0500
@@ -74,8 +74,6 @@
int stage_num = fs_req->getStageNum();
int seq_num = inst->seqNum;
- fs_req->fault = NoFault;
-
DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid,
pc[tid]);
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