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The summary line caught my eye and I had no idea what it really meant until I read the rest of the message. After reading it, I understood what you were trying to say. Perhaps saying something like "don't read register for update when overwriting all bits" Perhaps that's not any better though. src/arch/isa_parser.py <http://reviews.m5sim.org/r/464/#comment1195> I don't think you want this. - Nathan On 2011-02-03 03:22:26, Gabe Black wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/464/ > ----------------------------------------------------------- > > (Updated 2011-02-03 03:22:26) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > X86: Don't read in dest regs if all bits are replaced. > > In x86, 32 and 64 bit writes to registers in when registers appear to be 32 or > 64 bits wide overwrite all bits of the destination register. This change > removes false dependencies in these cases where the previous value of a > register doesn't need to be read to write a new value. New versions of most > microops are created that have a "Big" suffix which simply overwrite their > destination, and the right version to use is selected during microop > allocation based on the selected data size. > > This does not change the performance of the O3 CPU model significantly, I > assume because there are other false dependencies from the condition code bits > in the flags register. > > > Diffs > ----- > > src/arch/isa_parser.py 4afd05b9485e > src/arch/x86/isa/microops/ldstop.isa 4afd05b9485e > src/arch/x86/isa/microops/limmop.isa 4afd05b9485e > src/arch/x86/isa/microops/regop.isa 4afd05b9485e > > Diff: http://reviews.m5sim.org/r/464/diff > > > Testing > ------- > > > Thanks, > > Gabe > >
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