changeset 6220632e8636 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6220632e8636
description:
X86: Use all 64 bits of the lstar register in the SYSCALL_64 macroop.
During SYSCALL_64, use dataSize=8 when handling new rip (ref
http://www.intel.com/Assets/PDF/manual/253668.pdf 5.8.8 IA32_LSTAR is a
64-bit
address)
diffstat:
src/arch/x86/isa/insts/general_purpose/system_calls.py | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diffs (14 lines):
diff -r fb0a01641d73 -r 6220632e8636
src/arch/x86/isa/insts/general_purpose/system_calls.py
--- a/src/arch/x86/isa/insts/general_purpose/system_calls.py Mon Feb 07
15:12:59 2011 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/system_calls.py Mon Feb 07
15:16:27 2011 -0800
@@ -79,8 +79,8 @@
wrattr ss, t4
# Set the new rip.
- rdval t7, lstar
- wrip t0, t7
+ rdval t7, lstar, dataSize=8
+ wrip t0, t7, dataSize=8
# Mask the flags against sf_mask and leave RF turned off.
rdval t3, sf_mask, dataSize=8
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
