changeset e64e90b862a7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e64e90b862a7
description:
X86: Update stats for the reduced register reads.
diffstat:
tests/long/00.gzip/ref/x86/linux/o3-timing/simout | 8 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt | 710
++++----
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout | 6 +-
tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt | 10 +-
tests/long/00.gzip/ref/x86/linux/simple-timing/simout | 6 +-
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt | 10 +-
tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout | 9 +-
tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt | 10 +-
tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout | 9 +-
tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt | 10 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/simout | 8 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt | 736
++++----
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout | 6 +-
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt | 10 +-
tests/long/10.mcf/ref/x86/linux/simple-timing/simout | 6 +-
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt | 10 +-
tests/long/20.parser/ref/x86/linux/o3-timing/config.ini | 2 +-
tests/long/20.parser/ref/x86/linux/o3-timing/simout | 12 +-
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt | 744
+++++-----
tests/long/20.parser/ref/x86/linux/simple-atomic/simout | 6 +-
tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt | 10 +-
tests/long/20.parser/ref/x86/linux/simple-timing/simout | 6 +-
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt | 10 +-
tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout | 6 +-
tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt | 10 +-
tests/long/60.bzip2/ref/x86/linux/simple-timing/simout | 6 +-
tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt | 10 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/simout | 10 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt | 650
++++----
tests/long/70.twolf/ref/x86/linux/simple-atomic/simout | 8 +-
tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt | 10 +-
tests/long/70.twolf/ref/x86/linux/simple-timing/simout | 8 +-
tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt | 10 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/simout | 9 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt | 569 +++---
tests/quick/00.hello/ref/x86/linux/simple-atomic/simout | 6 +-
tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt | 10 +-
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats | 18 +-
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout | 6 +-
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt | 10 +-
tests/quick/00.hello/ref/x86/linux/simple-timing/simout | 6 +-
tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt | 8 +-
42 files changed, 1860 insertions(+), 1864 deletions(-)
diffs (truncated from 4839 to 300 lines):
diff -r b243dc8cec8b -r e64e90b862a7
tests/long/00.gzip/ref/x86/linux/o3-timing/simout
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout Sun Feb 13 17:44:24
2011 -0800
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout Sun Feb 13 17:44:32
2011 -0800
@@ -5,9 +5,9 @@
All Rights Reserved
-M5 compiled Feb 7 2011 02:32:07
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 02:32:13
+M5 compiled Feb 7 2011 20:06:49
+M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip
+M5 started Feb 7 2011 20:06:52
M5 executing on burrito
command line: build/X86_SE/m5.fast -d
build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py
build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@@ -1067,4 +1067,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 772390499500 because target called exit()
+Exiting @ tick 758990697000 because target called exit()
diff -r b243dc8cec8b -r e64e90b862a7
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt Sun Feb 13
17:44:24 2011 -0800
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt Sun Feb 13
17:44:32 2011 -0800
@@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 168346 #
Simulator instruction rate (inst/s)
-host_mem_usage 232444 #
Number of bytes of host memory used
-host_seconds 9631.89 #
Real time elapsed on the host
-host_tick_rate 80190939 #
Simulator tick rate (ticks/s)
+host_inst_rate 248801 #
Simulator instruction rate (inst/s)
+host_mem_usage 232880 #
Number of bytes of host memory used
+host_seconds 6517.22 #
Real time elapsed on the host
+host_tick_rate 116459266 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 1621493982 #
Number of instructions simulated
-sim_seconds 0.772390 #
Number of seconds simulated
-sim_ticks 772390499500 #
Number of ticks simulated
+sim_seconds 0.758991 #
Number of seconds simulated
+sim_ticks 758990697000 #
Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 126254885 #
Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 126894033 #
Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 123829137 #
Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 124444739 #
Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 #
Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 5933287 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 126894073 #
Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 126894073 #
Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 5933451 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 124445048 #
Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 124445048 #
Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 #
Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 107161579 #
Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3710402 #
number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 4428744 #
number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 1511501895
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.072770
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.173458
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 1488500908
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.089347
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.266465
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 505879323 33.47%
33.47% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 677452709 44.82%
78.29% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 153213861 10.14%
88.43% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 112394621 7.44%
95.86% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 32585093 2.16%
98.02% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 19016713 1.26%
99.27% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 5421676 0.36%
99.63% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 1827497 0.12%
99.75% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 3710402 0.25%
100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 544771983 36.60%
36.60% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 603082048 40.52%
77.11% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 142955782 9.60%
86.72% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 121627881 8.17%
94.89% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 42142525 2.83%
97.72% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 19097450 1.28%
99.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 4632040 0.31%
99.32% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 5762455 0.39%
99.70% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 4428744 0.30%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 1511501895
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 1488500908
# Number of insts commited each cycle
system.cpu.commit.COM:count 1621493982 #
Number of instructions committed
system.cpu.commit.COM:fp_insts 0 #
Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 #
Number of function calls committed.
@@ -44,422 +44,422 @@
system.cpu.commit.COM:membars 0 #
Number of memory barriers committed
system.cpu.commit.COM:refs 607228182 #
Number of memory references committed
system.cpu.commit.COM:swp_count 0 #
Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 5933318 #
The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 5933482 #
The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1621493982 #
The number of committed instructions
system.cpu.commit.commitNonSpecStalls 50 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 227874068 #
The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 174503493 #
The number of squashed insts skipped by commit
system.cpu.committedInsts 1621493982 #
Number of Instructions Simulated
system.cpu.committedInsts_total 1621493982 #
Number of Instructions Simulated
-system.cpu.cpi 0.952690 #
CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.952690 #
CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 326327666 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 10363.748203
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7391.735933
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 326125265 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2097633000 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000620 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 202401 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 1725 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1483344000
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000615 #
mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 200676 #
number of ReadReq MSHR misses
+system.cpu.cpi 0.936162 #
CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.936162 #
CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 328666076 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 10263.411891
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7269.320090
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 328458033 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 2135231000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000633 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 208043 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 1354 #
number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1502488500
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000629 #
mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 206689 #
number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 188186057 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 19667.198248
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10021.451346
# average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 186945733 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 24393698000 #
number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.006591 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1240324 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 994745 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2461058000
# number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.001305 #
mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 245579 #
number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 19664.658707
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9970.057484
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 186942755 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 24449109500 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.006607 #
miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1243302 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 995928 #
number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2466333000
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.001315 #
mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 247374 #
number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 15789.833755
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 1149.728625 #
Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles::no_targets 15814.402211
# average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 1135.086514 #
Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 29234 #
number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 29308 #
number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 461600000
# number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 463488500
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 514513723 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 18362.010085 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 8838.897043
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 513070998 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 26491331000 #
number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.002804 #
miss rate for demand accesses
-system.cpu.dcache.demand_misses 1442725 #
number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 996470 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 3944402000
# number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000867 #
mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 446255 #
number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 516852133 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 18317.037300 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 8740.684663
# average overall mshr miss latency
+system.cpu.dcache.demand_hits 515400788 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 26584340500 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002808 #
miss rate for demand accesses
+system.cpu.dcache.demand_misses 1451345 #
number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 997282 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 3968821500
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000879 #
mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 454063 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999781 #
Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4095.101758 #
Average occupied blocks per context
-system.cpu.dcache.overall_accesses 514513723 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 18362.010085
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 8838.897043
# average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.999777 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4095.087002 #
Average occupied blocks per context
+system.cpu.dcache.overall_accesses 516852133 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 18317.037300
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 8740.684663
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 513070998 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 26491331000 #
number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.002804 #
miss rate for overall accesses
-system.cpu.dcache.overall_misses 1442725 #
number of overall misses
-system.cpu.dcache.overall_mshr_hits 996470 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 3944402000
# number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000867 #
mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 446255 #
number of overall MSHR misses
+system.cpu.dcache.overall_hits 515400788 #
number of overall hits
+system.cpu.dcache.overall_miss_latency 26584340500 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002808 #
miss rate for overall accesses
+system.cpu.dcache.overall_misses 1451345 #
number of overall misses
+system.cpu.dcache.overall_mshr_hits 997282 #
number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 3968821500
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000879 #
mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 454063 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 442158 #
number of replacements
-system.cpu.dcache.sampled_refs 446254 #
Sample count of references to valid blocks.
+system.cpu.dcache.replacements 449967 #
number of replacements
+system.cpu.dcache.sampled_refs 454063 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.101758 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 513070998 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 331552000 #
Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 398281 #
number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 176333648 #
Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 1886463332 #
Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 320369444 #
Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 981528406 #
Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 33063147 #
Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 33270397 #
Number of cycles decode is unblocking
-system.cpu.fetch.Branches 126894073 #
Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 119630706 #
Number of cache lines fetched
-system.cpu.fetch.Cycles 1056772647 #
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 432705 #
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 1026147627 #
Number of instructions fetch has processed
+system.cpu.dcache.tagsinuse 4095.087002 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 515400788 #
Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 331273000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 403776 #
number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 134525635 #
Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 1844468999 #
Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 346793246 #
Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 965499551 #
Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 29266045 #
Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 41682476 #
Number of cycles decode is unblocking
+system.cpu.fetch.Branches 124445048 #
Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 129713560 #
Number of cache lines fetched
+system.cpu.fetch.Cycles 1050276779 #
Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 844154 #
Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 1022007635 #
Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 46 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
-system.cpu.fetch.SquashCycles 9324994 #
Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.082144 #
Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 119630706 #
Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 126254885 #
Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.664267 #
Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 1544565042 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.230490 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.292215 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.SquashCycles 12829021 #
Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.081981 #
Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 129713560 #
Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 123829137 #
Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.673268 #
Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 1517766953 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.229744 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.282154 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 522111775 33.80% 33.80% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 496583342 32.15% 65.95% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 273451194 17.70% 83.66% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 224891951 14.56% 98.22% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8280335 0.54% 98.75% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1557581 0.10% 98.85% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 722 0.00% 98.85% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 8665 0.00% 98.86% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 17679477 1.14% 100.00% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 499259849 32.89% 32.89% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 507370292 33.43% 66.32% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 273389808 18.01% 84.34% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 210662042 13.88% 98.22% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8152383 0.54% 98.75% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1243560 0.08% 98.83% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 720 0.00% 98.83% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 8664 0.00% 98.84% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 17679635 1.16% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1544565042 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 1517766953 #
Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 2 #
number of floating regfile reads
-system.cpu.icache.ReadReq_accesses 119630706 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 37171.926007
# average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35433.712121
# average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 119629787 #
number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 34161000 #
number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000008 #
miss rate for ReadReq accesses
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