> > > But I need to find the point to log order of completion of loads and stores > in the LSQ (between LSQ and L1 cache), to check the effect of that change. > I was observing inside LSQUnit<Impl>::completeDataAccess(PacketPtr pkt). > But the order observed doesn't look like the expected. > Looks like you are going to have to check the TSO (?) semantics here. Whose to say that if you issue a # of memory accesses in a particular order, that they finish in a particular order? Isn't caching (and locality of your memory accesses) going to determine this? Is it not OK that the memory accesses are sent to the memory system in a certain order but arent necessarily completed in a certain order? Again, you'll need to check the TSO or whatever constraints you are trying to enforce for that case.
-- - Korey
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