changeset 96bde0910197 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=96bde0910197
description:
merge alpha system files into tree
diffstat:
LICENSE
| 2 +-
README
| 32 +-
RELEASE_NOTES
| 136 -
configs/common/FSConfig.py
| 4 +
configs/example/ruby_fs.py
| 12 +-
configs/example/ruby_mem_test.py
| 6 +
ext/x11keysym/keysym.h
| 76 +
ext/x11keysym/keysymdef.h
| 2358 ++++++++++
src/SConscript
| 2 +-
src/arch/arm/table_walker.cc
| 17 +-
src/arch/arm/table_walker.hh
| 20 +-
src/arch/arm/tlb.cc
| 2 +
src/arch/generic/debugfaults.hh
| 111 +
src/arch/mips/isa/decoder.isa
| 16 +-
src/arch/x86/SConscript
| 1 +
src/arch/x86/insts/badmicroop.cc
| 55 +
src/arch/x86/insts/badmicroop.hh
| 52 +
src/arch/x86/insts/macroop.hh
| 7 +-
src/arch/x86/insts/microregop.cc
| 3 -
src/arch/x86/isa/includes.isa
| 2 +
src/arch/x86/isa/microops/debug.isa
| 69 +-
src/arch/x86/isa/microops/ldstop.isa
| 78 +-
src/arch/x86/isa/microops/limmop.isa
| 27 +-
src/arch/x86/isa/microops/regop.isa
| 293 +-
src/arch/x86/microcode_rom.hh
| 7 +-
src/arch/x86/predecoder.hh
| 6 +-
src/arch/x86/types.hh
| 56 +-
src/base/SConscript
| 1 +
src/base/bitmap.cc
| 82 +
src/base/bitmap.hh
| 114 +
src/base/compiler.hh
| 2 +
src/base/vnc/SConscript
| 48 +
src/base/vnc/VncServer.py
| 45 +
src/base/vnc/convert.cc
| 139 +
src/base/vnc/convert.hh
| 141 +
src/base/vnc/vncserver.cc
| 703 ++
src/base/vnc/vncserver.hh
| 475 ++
src/cpu/base_dyn_inst.hh
| 125 +-
src/cpu/base_dyn_inst_impl.hh
| 15 +
src/cpu/inorder/SConscript
| 3 +-
src/cpu/inorder/cpu.cc
| 130 +-
src/cpu/inorder/cpu.hh
| 85 +
src/cpu/inorder/first_stage.cc
| 2 +-
src/cpu/inorder/inorder_dyn_inst.cc
| 30 +-
src/cpu/inorder/inorder_dyn_inst.hh
| 109 +-
src/cpu/inorder/pipeline_stage.cc
| 11 +-
src/cpu/inorder/pipeline_traits.cc
| 171 -
src/cpu/inorder/pipeline_traits.hh
| 18 +-
src/cpu/inorder/resource.cc
| 4 +-
src/cpu/inorder/resource_pool.cc
| 11 +
src/cpu/inorder/resource_pool.hh
| 2 +
src/cpu/inorder/resource_sked.cc
| 78 +-
src/cpu/inorder/resource_sked.hh
| 206 +-
src/cpu/inorder/resources/cache_unit.cc
| 62 +-
src/cpu/inorder/resources/decode_unit.cc
| 7 +-
src/cpu/inorder/resources/fetch_unit.cc
| 6 +-
src/cpu/inorder/resources/graduation_unit.cc
| 5 +-
src/cpu/inorder/resources/inst_buffer.cc
| 13 +-
src/cpu/inorder/resources/inst_buffer_new.cc
| 158 -
src/cpu/inorder/resources/inst_buffer_new.hh
| 109 -
src/cpu/inorder/resources/mult_div_unit.cc
| 6 +-
src/cpu/inorder/resources/tlb_unit.cc
| 2 +-
src/cpu/inorder/resources/use_def.cc
| 6 +-
src/cpu/o3/fetch.hh
| 4 +
src/cpu/o3/fetch_impl.hh
| 23 +-
src/cpu/o3/iew_impl.hh
| 21 +
src/cpu/o3/inst_queue.hh
| 28 +
src/cpu/o3/inst_queue_impl.hh
| 53 +-
src/cpu/o3/lsq_unit_impl.hh
| 10 +-
src/cpu/simple/timing.cc
| 12 +-
src/cpu/simple/timing.hh
| 7 +
src/cpu/translation.hh
| 32 +-
src/dev/SConscript
| 1 +
src/dev/arm/RealView.py
| 24 +-
src/dev/arm/amba_device.cc
| 8 +
src/dev/arm/amba_device.hh
| 13 +
src/dev/arm/kmi.cc
| 270 +-
src/dev/arm/kmi.hh
| 101 +-
src/dev/arm/pl111.cc
| 600 +-
src/dev/arm/pl111.hh
| 178 +-
src/dev/arm/rv_ctrl.cc
| 30 +
src/dev/arm/rv_ctrl.hh
| 10 +-
src/dev/arm/timer_sp804.cc
| 6 +-
src/dev/ps2.cc
| 200 +
src/dev/ps2.hh
| 94 +
src/mem/protocol/MESI_CMP_directory-L1cache.sm
| 35 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
| 32 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm
| 35 +-
src/mem/protocol/MOESI_hammer-cache.sm
| 57 +-
src/mem/ruby/buffers/MessageBuffer.cc
| 3 +
src/mem/ruby/buffers/MessageBuffer.hh
| 6 +
src/mem/ruby/common/Consumer.hh
| 1 +
src/mem/ruby/network/simple/PerfectSwitch.cc
| 285 +-
src/mem/ruby/network/simple/PerfectSwitch.hh
| 2 +
src/mem/ruby/slicc_interface/Message.hh
| 2 +
src/mem/ruby/slicc_interface/NetworkMessage.hh
| 7 +
src/mem/ruby/system/RubyPort.cc
| 1 -
src/python/m5/main.py
| 9 -
src/sim/root.cc
| 13 +-
src/sim/root.hh
| 17 +-
src/sim/serialize.cc
| 56 +-
src/sim/serialize.hh
| 8 +
src/sim/tlb.hh
| 18 +
tests/configs/memtest-ruby.py
| 6 +
tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
| 2 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/simout
| 10 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
| 736 +-
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
| 6 +-
tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
| 10 +-
tests/long/00.gzip/ref/x86/linux/simple-timing/simout
| 6 +-
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
| 10 +-
tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
| 9 +-
tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
| 10 +-
tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
| 9 +-
tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
| 10 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
| 2 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/simout
| 10 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
| 749 +-
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
| 6 +-
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
| 10 +-
tests/long/10.mcf/ref/x86/linux/simple-timing/simout
| 6 +-
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
| 10 +-
tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
| 2 +-
tests/long/20.parser/ref/x86/linux/o3-timing/simout
| 14 +-
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
| 774 +-
tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
| 2 +-
tests/long/20.parser/ref/x86/linux/simple-atomic/simout
| 8 +-
tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
| 10 +-
tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
| 2 +-
tests/long/20.parser/ref/x86/linux/simple-timing/simout
| 8 +-
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
| 10 +-
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
| 8 +-
tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
| 6 +-
tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
| 10 +-
tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
| 6 +-
tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
| 10 +-
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
| 8 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
| 2 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/simout
| 12 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
| 719 +-
tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
| 8 +-
tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
| 10 +-
tests/long/70.twolf/ref/x86/linux/simple-timing/simout
| 8 +-
tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
| 10 +-
tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
| 8 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
| 14 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
| 28 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
| 8 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
| 26 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
| 68 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
| 54 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
| 8 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
| 26 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
| 68 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
| 92 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
| 8 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
| 24 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
| 97 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
| 164 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
| 10 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
| 30 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
| 14 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
| 26 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
| 8 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
| 26 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
| 68 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
| 54 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
| 8 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
| 26 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
| 68 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
| 60 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
| 8 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
| 24 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
| 99 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
| 164 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
| 10 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
| 30 +-
tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
| 8 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/simout
| 11 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
| 684 +-
tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
| 6 +-
tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
| 10 +-
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
| 18 +-
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
| 6 +-
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
| 10 +-
tests/quick/00.hello/ref/x86/linux/simple-timing/simout
| 6 +-
tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
| 8 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
| 44 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
| 2 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
| 12 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 340 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
| 44 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
| 2 +
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
| 12 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 526 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
| 0
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
| 35 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
| 691 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
| 146 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
| 10 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
| 42 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
| 46 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
| 977 ++-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
| 146 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
| 10 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
| 42 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
| 46 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
| 1156 ++--
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
| 146 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
| 10 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
| 40 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
| 47 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
| 979 ++-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
| 146 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
| 10 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
| 40 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
| 12 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
| 28 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
| 8 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
| 6 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
| 71 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
| 46 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
| 8 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
| 6 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
| 71 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
| 485 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
| 10 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
| 10 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
| 102 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
| 353 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
| 10 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
| 10 +-
util/make_release.py
| 222 -
233 files changed, 13688 insertions(+), 7860 deletions(-)
diffs (truncated from 30975 to 300 lines):
diff -r 3b16b17cde7f -r 96bde0910197 LICENSE
--- a/LICENSE Wed Feb 16 00:34:02 2011 -0600
+++ b/LICENSE Wed Feb 16 10:57:04 2011 -0500
@@ -1,4 +1,4 @@
-Copyright (c) 2000-2008 The Regents of The University of Michigan
+Copyright (c) 2000-2011 The Regents of The University of Michigan
All rights reserved.
Redistribution and use in source and binary forms, with or without
diff -r 3b16b17cde7f -r 96bde0910197 README
--- a/README Wed Feb 16 00:34:02 2011 -0600
+++ b/README Wed Feb 16 10:57:04 2011 -0500
@@ -1,4 +1,4 @@
-This is release 2.0_beta6 of the M5 simulator.
+This is the M5 simulator.
For detailed information about building the simulator and getting
started please refer to http://www.m5sim.org.
@@ -9,13 +9,16 @@
Short version:
-1. If you don't have SCons version 0.96.91 or newer, get it from
+1. If you don't have SCons version 0.98.1 or newer, get it from
http://wwww.scons.org.
-2. If you don't have SWIG version 1.3.28 or newer, get it from
+2. If you don't have SWIG version 1.3.31 or newer, get it from
http://wwww.swig.org.
-3. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'. This
+3. Make sure you also have gcc version 3.4.6 or newer, Python 2.4 or newer
+(the dev version with header files), zlib, and the m4 preprocessor.
+
+4. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'. This
will build the debug version of the m5 binary (m5.debug) for the Alpha
syscall emulation target, and run the quick regression tests on it.
@@ -25,18 +28,21 @@
-------------------------
The basic source release includes these subdirectories:
- - m5:
+ - m5:
+ - configs: simulation configuration scripts
+ - ext: less-common external packages needed to build m5
- src: source code of the m5 simulator
+ - system: source for some optional system software for simulated systems
- tests: regression tests
- - ext: less-common external packages needed to build m5
+ - util: useful utility programs and files
-To run full-system simulations, you will need compiled console,
-PALcode, and kernel binaries and one or more disk images. These files
-are collected in a separate archive, m5_system.tar.bz2. This file
-can he downloaded separately.
+To run full-system simulations, you will need compiled system firmware
+(console and PALcode for Alpha), kernel binaries and one or more disk images.
+These files for Alpha are collected in a separate archive, m5_system.tar.bz2.
+This file can he downloaded separately.
-M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP
-Tru64 version of Unix. We are able to distribute Linux and FreeBSD
-bootdisks, but we are unable to distribute bootable disk images of
+Depending on the ISA used, M5 may support Linux 2.4/2.6, FreeBSD, and the
+proprietary Compaq/HP Tru64 version of Unix. We are able to distribute Linux
+and FreeBSD bootdisks, but we are unable to distribute bootable disk images of
Tru64 Unix. If you have a Tru64 license and are interested in
obtaining disk images, contact us at m5-us...@m5sim.org
diff -r 3b16b17cde7f -r 96bde0910197 RELEASE_NOTES
--- a/RELEASE_NOTES Wed Feb 16 00:34:02 2011 -0600
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,149 +0,0 @@
-October 6, 2008: m5_2.0_beta6
---------------------
-New Features
-1. Support for gcc 4.3
-2. Core m5 code in libm5 for integration with other simulators
-3. Preliminary support for X86 SE mode
-4. Additional system calls emulated
-5. m5term updated to work on OS X
-6. Ability to disable listen sockets
-7. Event queue performance improvements and rewrite
-8. Better errors for unconnected memory ports
-
-Bug fixes
-1. ALPHA_SE O3 perlbmk benchmark
-2. Translation bug where O3 could fetch from uncachable memory
-3. Many minor bugs
-
-Outstanding issues for 2.0 release:
---------------------
-1. Statistics cleanup
-2. Improve regression system
-3. Testing
-4. Validation
-
-March 1, 2008: m5_2.0_beta5
---------------------
-New Features
-1. Rick Strong's Simpoints config changes
-2. Support for FSU ARM port
-3. EXTRAS= option allow architectures to be specified
-
-Bug fixes
-1. Bus timing more realistic
-2. Cache writeback, LL/SC fixes
-3. Minor IGbE NIC fixes
-4. O3 op latency fix
-5. SPARC TLB demap fixes
-6. SPARC SE memory layout fixes
-7. Variety of MIPS fixes
-
-Nov 4, 2007: m5_2.0_beta4
---------------------
-New Features
-1. New cache model
-2. Use of a I/O cache between devices and memory
-3. Ability to include compiled code with EXTRAS=
-4. Python creation of params structures for initialization
-5. Ability to remotely debug in SE
-
-Bug fixes:
-1. Fix SE serialization
-2. SPARC_FS booting with TimingSimpleCPU
-3. Rename cycles() to ticks()
-4. Various SPARC ISA fixes
-5. Draining code for checkpointing
-6. Various performance improvements
-
-Possible Incompatibilities:
-1. Real TLBs are now used in SE mode. This is more accurate however it could
- cause some problems if you've modified the way page handling is done in
- SE mode.
-2. There have been many changes to the way the SCons files work. SimObjects,
- sources files, and trace flags are all specified in the SConscript files.
- To see how to add your sources take a look at one of them.
-3. Python is now used to created the parameter structs that were created
- manually before. The parameters listed in a py file are turned into
- a header file with the same name (e.g. BadDevice.py -> BadDevice.hh).
- With this change the structs can be populated automatically and the
- ugly macros to define and create SimObjects at the bottem of source
- files are gone. The parameter structs also automatically inherit
- parameters from their parents.
-
-May 16, 2007: m5_2.0_beta3
---------------------
-New Features
-1. Some support for SPARC full-system simulation
-2. Reworking of trace facitities (parameter names changed, variadic macros
- removed)
-3. Scons script cleanups
-4. Some support for compiling with Intel CC
-
-Bug fixes since beta 2:
-1. Many SPARC linux syscall emulation support fixes
-2. Multiprocessor linux boot using the detailed O3 CPU module
-3. Workaround for DMA bug (final solution to be released with 2.0f)
-4. Simulator performance and memory leak fixes
-5. Fixed issue where console could stop printing in ALPHA_FS
-6. Fix issues with remote debugging
-7. Several compile fixes, including gcc 4.1
-8. Many other minor fixes and enhancements
-
-Nov. 28, 2006: m5_2.0_beta2
---------------------
-Bug fixes since beta 1:
-1. Many cache issues resolved
-2. Uni-coherence fixes in full-system
-3. LL/SC Support
-4. Draining/Switchover
-5. Functional Accesses
-6. Bus now has real timing
-7. Single config file for all SpecCPU2000 benchmarks
-8. Several other minor bug fixes and enhancements
-
-Aug. 25, 2006: m5_2.0_beta patch 1
---------------------
-Handful of minor bug fixes for m5_2.0_beta,
-along with a few new regression tests.
-
-Aug. 15, 2006: m5_2.0_beta
---------------------
-Major update to M5 including:
-- New CPU model
-- New memory system
-- More extensive python integration
-- Preliminary syscall emulation support for MIPS and SPARC
-This is a *beta* release, meaning that some features are not complete,
-and some features from M5 1.X aren't currently supported (e.g., MP
-coherence). We are working to address these limitations and hope to
-have a complete 2.0 release soon.
-
-Oct. 8, 2005: m5_1.1
---------------------
-Update release for IOSCA workshop mini-tutorial. New features include:
-- Preliminary FreeBSD support
-- Integration of regression tests into scons build framework
-- Several bug fixes and better compatibility for Cygwin hosts
-- Major cleanup of Alpha system code (console, PAL, etc.) to make
- it easier for others to build/modify
-- Fixes to enable compilation under g++ 4.0
-- Numerous minor bug fixes
-
-June 10, 2005: m5_1.0_web
--------------------------
-The 1.0 release posted on Sourceforge after the ISCA tutorial contains
-just a few very minor fixes relative to the CD.
-
-June 5, 2005: m5_1.0_tutorial
------------------------------
-First non-beta release. This release was on the CD distributed at the
-ISCA tutorial. Major enhancements relative to beta releases include
-Linux support and Python-based configuration language.
-
-June 17, 2004: m5_1.0_beta2
----------------------------
-Stealth-mode beta bug-fix update, not widely advertised.
-
-Oct. 17, 2003: m5_1.0_beta1
----------------------------
-Early beta release.
diff -r 3b16b17cde7f -r 96bde0910197 configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Wed Feb 16 00:34:02 2011 -0600
+++ b/configs/common/FSConfig.py Wed Feb 16 10:57:04 2011 -0500
@@ -238,6 +238,7 @@
self.intrctrl = IntrControl()
self.terminal = Terminal()
+ self.vncserver = VncServer()
self.kernel = binary('vmlinux.arm')
self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480' +
\
' norandmaps slram=slram0,0x8000000,+0x8000000' +
\
@@ -334,6 +335,9 @@
# Create and connect the busses required by each memory system
if Ruby:
connectX86RubySystem(self)
+ # add the ide to the list of dma devices that later need to attach to
+ # dma controllers
+ self._dma_devices = [self.pc.south_bridge.ide]
else:
connectX86ClassicSystem(self)
diff -r 3b16b17cde7f -r 96bde0910197 configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.py Wed Feb 16 00:34:02 2011 -0600
+++ b/configs/example/ruby_fs.py Wed Feb 16 10:57:04 2011 -0500
@@ -111,19 +111,17 @@
if buildEnv['TARGET_ISA'] == "alpha":
system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
- system.ruby = Ruby.create_system(options,
- system,
- system.piobus,
- system.dma_devices)
elif buildEnv['TARGET_ISA'] == "x86":
system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True)
setWorkCountOptions(system, options)
- system.ruby = Ruby.create_system(options,
- system,
- system.piobus)
else:
fatal("incapable of building non-alpha or non-x86 full system!")
+system.ruby = Ruby.create_system(options,
+ system,
+ system.piobus,
+ system._dma_devices)
+
system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
for (i, cpu) in enumerate(system.cpu):
diff -r 3b16b17cde7f -r 96bde0910197 configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py Wed Feb 16 00:34:02 2011 -0600
+++ b/configs/example/ruby_mem_test.py Wed Feb 16 10:57:04 2011 -0500
@@ -135,6 +135,12 @@
cpu.test = system.ruby.cpu_ruby_ports[i].port
cpu.functional = system.funcmem.port
+ #
+ # Since the memtester is incredibly bursty, increase the deadlock
+ # threshold to 5 million cycles
+ #
+ system.ruby.cpu_ruby_ports[i].deadlock_threshold = 5000000
+
for (i, dma) in enumerate(dmas):
#
# Tie the dma memtester ports to the correct functional port
diff -r 3b16b17cde7f -r 96bde0910197 ext/x11keysym/keysym.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/ext/x11keysym/keysym.h Wed Feb 16 10:57:04 2011 -0500
@@ -0,0 +1,76 @@
+/* $Xorg: keysym.h,v 1.4 2001/02/09 02:03:23 xorgcvs Exp $ */
+
+/***********************************************************
+
+Copyright 1987, 1998 The Open Group
+
+Permission to use, copy, modify, distribute, and sell this software and its
+documentation for any purpose is hereby granted without fee, provided that
+the above copyright notice appear in all copies and that both that
_______________________________________________
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
