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Ship it! Overall the patch looks good to me. src/mem/slicc/ast/StateDeclAST.py <http://reviews.m5sim.org/r/496/#comment1249> The copyright needs to be changed. src/mem/slicc/ast/TypeFieldStateAST.py <http://reviews.m5sim.org/r/496/#comment1250> The copyright needs to be changed. - Nilay On 2011-02-22 14:36:11, Brad Beckmann wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/496/ > ----------------------------------------------------------- > > (Updated 2011-02-22 14:36:11) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > ruby: automate permission setting > > This patch integrates permissions with cache and memory states, and then > automates the setting of permissions within the generated code. No longer > does one need to manually set the permissions within the setState funciton. > This patch will faciliate easier functional access support by always correctly > setting permissions for both cache and memory states. > > > Diffs > ----- > > src/mem/protocol/MESI_CMP_directory-L1cache.sm e6ce478c05d3 > src/mem/protocol/MESI_CMP_directory-L2cache.sm e6ce478c05d3 > src/mem/protocol/MESI_CMP_directory-dir.sm e6ce478c05d3 > src/mem/protocol/MESI_CMP_directory-dma.sm e6ce478c05d3 > src/mem/protocol/MI_example-cache.sm e6ce478c05d3 > src/mem/protocol/MI_example-dir.sm e6ce478c05d3 > src/mem/protocol/MI_example-dma.sm e6ce478c05d3 > src/mem/protocol/MOESI_CMP_directory-L1cache.sm e6ce478c05d3 > src/mem/protocol/MOESI_CMP_directory-L2cache.sm e6ce478c05d3 > src/mem/protocol/MOESI_CMP_directory-dir.sm e6ce478c05d3 > src/mem/protocol/MOESI_CMP_directory-dma.sm e6ce478c05d3 > src/mem/protocol/MOESI_CMP_token-L1cache.sm e6ce478c05d3 > src/mem/protocol/MOESI_CMP_token-L2cache.sm e6ce478c05d3 > src/mem/protocol/MOESI_CMP_token-dir.sm e6ce478c05d3 > src/mem/protocol/MOESI_CMP_token-dma.sm e6ce478c05d3 > src/mem/protocol/MOESI_hammer-cache.sm e6ce478c05d3 > src/mem/protocol/MOESI_hammer-dir.sm e6ce478c05d3 > src/mem/protocol/MOESI_hammer-dma.sm e6ce478c05d3 > src/mem/protocol/RubySlicc_Types.sm e6ce478c05d3 > src/mem/ruby/slicc_interface/AbstractCacheEntry.hh e6ce478c05d3 > src/mem/ruby/slicc_interface/AbstractCacheEntry.cc e6ce478c05d3 > src/mem/ruby/slicc_interface/AbstractEntry.hh e6ce478c05d3 > src/mem/ruby/slicc_interface/AbstractEntry.cc e6ce478c05d3 > src/mem/slicc/ast/StateDeclAST.py PRE-CREATION > src/mem/slicc/ast/TypeFieldEnumAST.py e6ce478c05d3 > src/mem/slicc/ast/TypeFieldStateAST.py PRE-CREATION > src/mem/slicc/ast/__init__.py e6ce478c05d3 > src/mem/slicc/parser.py e6ce478c05d3 > src/mem/slicc/symbols/StateMachine.py e6ce478c05d3 > src/mem/slicc/symbols/Type.py e6ce478c05d3 > > Diff: http://reviews.m5sim.org/r/496/diff > > > Testing > ------- > > > Thanks, > > Brad > >
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