changeset 5a8208fa1600 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5a8208fa1600
description:
configs: cache: add cache line size option
diffstat:
configs/common/CacheConfig.py | 9 ++++++---
configs/common/Options.py | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
diffs (37 lines):
diff -r 8fe2d7ff1111 -r 5a8208fa1600 configs/common/CacheConfig.py
--- a/configs/common/CacheConfig.py Wed Feb 23 01:01:46 2011 -0500
+++ b/configs/common/CacheConfig.py Wed Feb 23 14:26:55 2011 -0500
@@ -35,7 +35,8 @@
def config_cache(options, system):
if options.l2cache:
- system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc)
+ system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
+ block_size=options.cacheline_size)
system.tol2bus = Bus()
system.l2.cpu_side = system.tol2bus.port
system.l2.mem_side = system.membus.port
@@ -43,8 +44,10 @@
for i in xrange(options.num_cpus):
if options.caches:
- icache = L1Cache(size = options.l1i_size, assoc =
options.l1i_assoc)
- dcache = L1Cache(size = options.l1d_size, assoc =
options.l1d_assoc)
+ icache = L1Cache(size = options.l1i_size, assoc =
options.l1i_assoc,
+ block_size=options.cacheline_size)
+ dcache = L1Cache(size = options.l1d_size, assoc =
options.l1d_assoc,
+ block_size=options.cacheline_size)
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(),
diff -r 8fe2d7ff1111 -r 5a8208fa1600 configs/common/Options.py
--- a/configs/common/Options.py Wed Feb 23 01:01:46 2011 -0500
+++ b/configs/common/Options.py Wed Feb 23 14:26:55 2011 -0500
@@ -46,6 +46,7 @@
parser.add_option("--l1i_assoc", type="int", default=2)
parser.add_option("--l2_assoc", type="int", default=8)
parser.add_option("--l3_assoc", type="int", default=16)
+parser.add_option("--cacheline_size", type="int", default=64)
# Run duration options
parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
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