changeset 3bf9cdcfc4ee in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3bf9cdcfc4ee
description:
ARM: Reset simulation statistics when pref counters are reset.
The ARM performance counters are not currently supported by the model.
This patch interprets a 'reset performance counters' command to mean
'reset
the simulator statistics' instead.
diffstat:
src/arch/arm/isa.cc | 13 +++++++++++++
1 files changed, 13 insertions(+), 0 deletions(-)
diffs (30 lines):
diff -r a259ab86cabf -r 3bf9cdcfc4ee src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Wed Feb 23 15:10:48 2011 -0600
+++ b/src/arch/arm/isa.cc Wed Feb 23 15:10:48 2011 -0600
@@ -40,6 +40,7 @@
#include "arch/arm/isa.hh"
#include "sim/faults.hh"
+#include "sim/stat_control.hh"
namespace ArmISA
{
@@ -393,6 +394,18 @@
warn("Not doing anything for write of miscreg ACTLR\n");
break;
case MISCREG_PMCR:
+ {
+ // Performance counters not implemented. Instead, interpret
+ // a reset command to this register to reset the simulator
+ // statistics.
+ // PMCR_E | PMCR_P | PMCR_C
+ const int ResetAndEnableCounters = 0x7;
+ if (newVal == ResetAndEnableCounters) {
+ inform("Resetting all simobject stats\n");
+ Stats::schedStatEvent(false, true);
+ break;
+ }
+ }
case MISCREG_PMCCNTR:
case MISCREG_PMSELR:
warn("Not doing anything for write to miscreg %s\n",
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