changeset 9dc17725f795 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=9dc17725f795 description: ARM: Update regression tests for preceeding changes.
diffstat: tests/long/00.gzip/ref/arm/linux/o3-timing/simerr | 86 - tests/long/00.gzip/ref/arm/linux/o3-timing/simout | 12 +- tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt | 384 ++-- tests/long/10.mcf/ref/arm/linux/o3-timing/simout | 12 +- tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt | 348 ++-- tests/long/20.parser/ref/arm/linux/o3-timing/simerr | 82 - tests/long/20.parser/ref/arm/linux/o3-timing/simout | 12 +- tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt | 724 +++++----- tests/long/30.eon/ref/arm/linux/o3-timing/simerr | 108 - tests/long/30.eon/ref/arm/linux/o3-timing/simout | 12 +- tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt | 404 ++-- tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr | 2 - tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout | 12 +- tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 372 ++-- tests/long/50.vortex/ref/arm/linux/o3-timing/simerr | 12 - tests/long/50.vortex/ref/arm/linux/o3-timing/simout | 12 +- tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt | 428 ++-- tests/long/60.bzip2/ref/arm/linux/o3-timing/simout | 12 +- tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 678 ++++---- tests/long/70.twolf/ref/arm/linux/o3-timing/simout | 16 +- tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt | 348 ++-- tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini | 2 +- tests/quick/00.hello/ref/arm/linux/o3-timing/simout | 12 +- tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt | 444 +++--- tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout | 8 +- tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt | 12 +- tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status | 2 +- tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout | 8 +- tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 12 +- tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status | 2 +- 30 files changed, 2144 insertions(+), 2434 deletions(-) diffs (truncated from 6602 to 300 lines): diff -r 7544ad480a38 -r 9dc17725f795 tests/long/00.gzip/ref/arm/linux/o3-timing/simerr --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr Wed Feb 23 15:10:50 2011 -0600 +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr Wed Feb 23 15:10:50 2011 -0600 @@ -1,89 +1,3 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd -warn: Bad interworking branch address 0x7002. -For more information see: http://www.m5sim.org/warn/55f199fd hack: be nice to actually delete the event here diff -r 7544ad480a38 -r 9dc17725f795 tests/long/00.gzip/ref/arm/linux/o3-timing/simout --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Wed Feb 23 15:10:50 2011 -0600 +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Wed Feb 23 15:10:50 2011 -0600 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Feb 7 2011 01:56:16 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:59:50 -M5 executing on burrito -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing +M5 compiled Feb 21 2011 14:34:16 +M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch +M5 started Feb 21 2011 14:34:24 +M5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -43,4 +43,4 @@ Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 216988313500 because target called exit() +Exiting @ tick 216988269500 because target called exit() diff -r 7544ad480a38 -r 9dc17725f795 tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Wed Feb 23 15:10:50 2011 -0600 +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Wed Feb 23 15:10:50 2011 -0600 @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 115233 # Simulator instruction rate (inst/s) -host_mem_usage 238284 # Number of bytes of host memory used -host_seconds 5211.87 # Real time elapsed on the host -host_tick_rate 41633525 # Simulator tick rate (ticks/s) +host_inst_rate 84615 # Simulator instruction rate (inst/s) +host_mem_usage 256696 # Number of bytes of host memory used +host_seconds 7097.77 # Real time elapsed on the host +host_tick_rate 30571310 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 600581394 # Number of instructions simulated +sim_insts 600581343 # Number of instructions simulated sim_seconds 0.216988 # Number of seconds simulated -sim_ticks 216988313500 # Number of ticks simulated +sim_ticks 216988269500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 80605282 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 86770000 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 80605280 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 86769998 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 3926724 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 92457745 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 92457745 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 92457743 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 92457743 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 70067581 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 7237695 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 7237688 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 415629341 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.444993 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.803103 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 415627277 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.445000 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.803105 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 151329728 36.41% 36.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 131463070 31.63% 68.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 59591076 14.34% 82.38% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 151327612 36.41% 36.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 131463127 31.63% 68.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 59591085 14.34% 82.38% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::3 19300079 4.64% 87.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 16801344 4.04% 91.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 14774924 3.55% 94.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 12865596 3.10% 97.71% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 2265829 0.55% 98.26% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 7237695 1.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 16801337 4.04% 91.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 14774918 3.55% 94.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 12865599 3.10% 97.71% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 2265832 0.55% 98.26% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 7237688 1.74% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 415629341 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 415627277 # Number of insts commited each cycle system.cpu.commit.COM:count 600581394 # Number of instructions committed system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,70 +44,70 @@ system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 219174038 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4754911 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4754311 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 600581394 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 3642 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 121350527 # The number of squashed insts skipped by commit -system.cpu.committedInsts 600581394 # Number of Instructions Simulated -system.cpu.committedInsts_total 600581394 # Number of Instructions Simulated +system.cpu.commit.commitSquashedInsts 121349980 # The number of squashed insts skipped by commit +system.cpu.committedInsts 600581343 # Number of Instructions Simulated +system.cpu.committedInsts_total 600581343 # Number of Instructions Simulated system.cpu.cpi 0.722594 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.722594 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 140357692 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13127.051417 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7797.439109 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 140121331 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3102723000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 13126.895414 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7797.393105 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 140121332 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3102673000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001684 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 236361 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 40726 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1525452000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 236360 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 40725 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1525443000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001394 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 195635 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 17787.356145 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10360.258061 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17787.364223 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10360.276216 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 67933393 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 26422494996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 26422506996 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.021399 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1485465 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 1237601 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2567935004 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2567939504 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 247864 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs 4386.427788 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 469.123189 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 469.123191 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 2188 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 9597504 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 209776550 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 17147.620024 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9229.754755 # average overall mshr miss latency -system.cpu.dcache.demand_hits 208054724 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 29525217996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 17147.607914 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9229.744608 # average overall mshr miss latency +system.cpu.dcache.demand_hits 208054725 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 29525179996 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.008208 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1721826 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1278327 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4093387004 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 1721825 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1278326 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4093382504 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 443499 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999739 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.932542 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 4094.932523 # Average occupied blocks per context system.cpu.dcache.overall_accesses 209776550 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 17147.620024 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9229.754755 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 17147.607914 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9229.744608 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 208054724 # number of overall hits -system.cpu.dcache.overall_miss_latency 29525217996 # number of overall miss cycles +system.cpu.dcache.overall_hits 208054725 # number of overall hits +system.cpu.dcache.overall_miss_latency 29525179996 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.008208 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1721826 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1278327 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4093387004 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 1721825 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1278326 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4093382504 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 443499 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -115,16 +115,16 @@ system.cpu.dcache.replacements 439401 # number of replacements system.cpu.dcache.sampled_refs 443497 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.932542 # Cycle average of tags in use -system.cpu.dcache.total_refs 208054727 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 90722000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4094.932523 # Cycle average of tags in use +system.cpu.dcache.total_refs 208054728 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 90723000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 394050 # number of writebacks _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
