changeset 03ee2388ea9d in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=03ee2388ea9d description: inorder: add 00.gzip and 60.bzip2 regression tests
diffstat: tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini | 234 +++++++ tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr | 11 + tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout | 47 + tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt | 301 +++++++++ tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini | 234 +++++++ tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr | 11 + tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout | 33 + tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt | 303 ++++++++++ 8 files changed, 1174 insertions(+), 0 deletions(-) diffs (truncated from 1206 to 300 lines): diff -r 2dfacb598d6d -r 03ee2388ea9d tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini Wed Feb 23 16:35:25 2011 -0500 @@ -0,0 +1,234 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 + +[system.cpu] +type=InOrderCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +activity=0 +cachePorts=2 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +cpu_id=0 +dataMemPort=dcache_port +defer_registration=false +div16Latency=1 +div16RepeatRate=1 +div24Latency=1 +div24RepeatRate=1 +div32Latency=1 +div32RepeatRate=1 +div8Latency=1 +div8RepeatRate=1 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchBuffSize=4 +fetchMemPort=icache_port +functionTrace=false +functionTraceStart=0 +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +memBlockSize=64 +multLatency=1 +multRepeatRate=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +stageTracing=false +stageWidth=4 +system=system +threadModel=SMT +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff -r 2dfacb598d6d -r 03ee2388ea9d tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr Wed Feb 23 16:35:25 2011 -0500 @@ -0,0 +1,11 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff -r 2dfacb598d6d -r 03ee2388ea9d tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout Wed Feb 23 16:35:25 2011 -0500 @@ -0,0 +1,47 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 23 2011 05:47:47 +M5 revision Unknown +M5 started Feb 23 2011 05:49:05 +M5 executing on m55-001.pool +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
