On Feb 24, 2011, at 5:34 AM, Gabe Black wrote: > I'm making some progress getting X86_FS working in O3, and now I'm > running into a problem where it looks like a memory mapped register, > specifically a segment base register, isn't being handled properly. It > looks like the access is actually going to memory instead of being > redirected to the control register. Some other weird things may be going > on as well since the value being written is wrong but shows up in the > disassembly correctly, and only one write happens when in the simple CPU > there are two. Maybe store coalescing of some sort? I dug around in O3's > source a bit and couldn't find anywhere the memory mapped IPR flag was > being checked, so O3 may be oblivious to this sort of thing. That's > surprising since I -thought- it already supported that. In retrospect I > don't know that I had any good reason to think that. I think you added > that mechanism, Ali. Any idea what's going on? Will I have to implement > that support? I don't think it's supported in O3. ARM doesn't use it and we never did SPARC_FS on o3, so I don't know when it would have gotten implemented.
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