changeset 4a59661d3fd1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4a59661d3fd1
description:
O3CPU: Fix iqCount and lsqCount SMT fetch policies.
Fixes two of the SMT fetch policies in O3CPU that were returning the
count
of instructions in the IQ or LSQ rather than the thread ID to fetch
from.
diffstat:
src/cpu/o3/fetch_impl.hh | 18 ++++++++++++------
1 files changed, 12 insertions(+), 6 deletions(-)
diffs (55 lines):
diff -r ac1bd3d1aa54 -r 4a59661d3fd1 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Thu Feb 24 02:14:45 2011 -0800
+++ b/src/cpu/o3/fetch_impl.hh Fri Feb 25 13:50:29 2011 +0000
@@ -1404,19 +1404,22 @@
ThreadID
DefaultFetch<Impl>::iqCount()
{
- std::priority_queue<ThreadID> PQ;
+ std::priority_queue<unsigned> PQ;
+ std::map<unsigned, ThreadID> threadMap;
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
ThreadID tid = *threads++;
+ unsigned iqCount = fromIEW->iewInfo[tid].iqCount;
- PQ.push(fromIEW->iewInfo[tid].iqCount);
+ PQ.push(iqCount);
+ threadMap[iqCount] = tid;
}
while (!PQ.empty()) {
- ThreadID high_pri = PQ.top();
+ ThreadID high_pri = threadMap[PQ.top()];
if (fetchStatus[high_pri] == Running ||
fetchStatus[high_pri] == IcacheAccessComplete ||
@@ -1434,19 +1437,22 @@
ThreadID
DefaultFetch<Impl>::lsqCount()
{
- std::priority_queue<ThreadID> PQ;
+ std::priority_queue<unsigned> PQ;
+ std::map<unsigned, ThreadID> threadMap;
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
ThreadID tid = *threads++;
+ unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount;
- PQ.push(fromIEW->iewInfo[tid].ldstqCount);
+ PQ.push(ldstqCount);
+ threadMap[ldstqCount] = tid;
}
while (!PQ.empty()) {
- ThreadID high_pri = PQ.top();
+ ThreadID high_pri = threadMap[PQ.top()];
if (fetchStatus[high_pri] == Running ||
fetchStatus[high_pri] == IcacheAccessComplete ||
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev