Hi Nilay, What exactly are you referring to as the "underlying processor"? Are you referring to real silicon?
Actual hardware doesn't support functional accesses. Functional accesses are unique to gem5 and are completely fake when compared to actual hardware. gem5 could support functional accesses by quiescing the system and then perform the read or write using the existing timing path. That would probably be a suitable solution if gdb running on the simulated system was the only source of dynamic functional accesses. However, there are other sources of dynamic functional accesses and we don't want to always perturb the system when performing those accesses. Thus we need a backdoor that doesn't perturb the system. Brad > -----Original Message----- > From: [email protected] [mailto:[email protected]] On > Behalf Of Nilay Vaish > Sent: Saturday, February 26, 2011 9:06 AM > To: M5 Developer List > Subject: Re: [m5-dev] Functional Access support in Ruby > > I was thinking about the behavior of functional accesses. Currently in > gdb > we can change the value of a program variable. Does that mean the > underlying processor supports functional accesses? If yes, then we > should > already have some knowledge about what is expected from functional > accesses. > > Nilay > > > On Fri, 25 Feb 2011, Beckmann, Brad wrote: > > > Yes, that is correct. The RubyPort::M5Port::recvFunctional() > function is where we need to add the new support. > > > > Brad > > > > > >> -----Original Message----- > >> From: [email protected] [mailto:[email protected]] > >> On Behalf Of Nilay Vaish > >> Sent: Friday, February 25, 2011 12:20 PM > >> To: [email protected] > >> Subject: [m5-dev] Functional Access support in Ruby > >> > >> Brad, > >> > >> Here is my understanding of the current state of functional accesses > in gem5. > >> As of now, all functional accesses are forwarded to the > PhysicalMemory's > >> MemoryPort. Instead, we would like to add > >> recvFunctional() function to M5Port of the RubyPort, and attach this > port as > >> peer instead of the PhysicalMemory. > >> > >> -- > >> Nilay > >> _______________________________________________ > >> m5-dev mailing list > >> [email protected] > >> http://m5sim.org/mailman/listinfo/m5-dev > > > > > > _______________________________________________ > > m5-dev mailing list > > [email protected] > > http://m5sim.org/mailman/listinfo/m5-dev > > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
