> On 2011-02-26 16:55:02, Gabe Black wrote: > > I see what you're doing here, I think. For the strategy your taking your > > implementation seems ok (other than some weird whitespace), but I'm not > > sure this is the way to go. The itstate should be part of the pc and then > > wouldn't depend on anything in the previous instruction. The way you've > > implemented this forced itstate stuff may be the real culprit. I don't > > remember all the details of our previous conversation about it, but I do > > remember suggesting a way to implement that that fit better with the rest > > of the pc state information and I expect would make this change unnecessary.
I'll keep that in mind... this is the last bug that I know about that mucks with IT state. If we do find some other issues I'll see if putting it state in the PC helps, but I'm pretty sure matt tried that without success. > On 2011-02-26 16:55:02, Gabe Black wrote: > > src/arch/arm/predecoder.hh, line 92 > > <http://reviews.m5sim.org/r/511/diff/1/?file=10544#file10544line92> > > > > Why all the extra blank lines? I went a little over board, I can clean them up. - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/511/#review909 ----------------------------------------------------------- On 2011-02-25 21:05:49, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/511/ > ----------------------------------------------------------- > > (Updated 2011-02-25 21:05:49) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Send instruction back to fetch on squash to seed predecoder correctly. > > > Diffs > ----- > > src/arch/alpha/predecoder.hh 9dc17725f795 > src/arch/arm/predecoder.hh 9dc17725f795 > src/arch/mips/predecoder.hh 9dc17725f795 > src/arch/power/predecoder.hh 9dc17725f795 > src/arch/sparc/predecoder.hh 9dc17725f795 > src/arch/x86/predecoder.hh 9dc17725f795 > src/cpu/o3/cpu.cc 9dc17725f795 > src/cpu/o3/fetch.hh 9dc17725f795 > src/cpu/o3/fetch_impl.hh 9dc17725f795 > > Diff: http://reviews.m5sim.org/r/511/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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