changeset a314f5c2caa0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a314f5c2caa0
description:
X86: Update X86_FS stats.
diffstat:
tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout | 11 +-
tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt | 351 ++--
tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout | 11 +-
tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt | 791
++++-----
4 files changed, 578 insertions(+), 586 deletions(-)
diffs (truncated from 1666 to 300 lines):
diff -r 021a0724c5c0 -r a314f5c2caa0
tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout Sun Feb
27 16:24:10 2011 -0800
+++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout Sun Feb
27 16:24:54 2011 -0800
@@ -5,12 +5,13 @@
All Rights Reserved
-M5 compiled Feb 8 2011 00:58:27
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb 8 2011 00:58:30
+M5 compiled Feb 26 2011 16:13:31
+M5 revision 412ef0f728a5 8092 default qtip tip updatefsstats.patch
+M5 started Feb 26 2011 16:13:35
M5 executing on burrito
-command line: build/X86_FS/m5.fast -d
build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-atomic -re
tests/run.py
build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-atomic
+command line: build/X86_FS/m5.opt -d
build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic -re
tests/run.py
build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+ 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5112051463500 because m5_exit instruction encountered
+Exiting @ tick 5112051446000 because m5_exit instruction encountered
diff -r 021a0724c5c0 -r a314f5c2caa0
tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt Sun Feb
27 16:24:10 2011 -0800
+++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt Sun Feb
27 16:24:54 2011 -0800
@@ -1,30 +1,30 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1892986 #
Simulator instruction rate (inst/s)
-host_mem_usage 370804 #
Number of bytes of host memory used
-host_seconds 214.81 #
Real time elapsed on the host
-host_tick_rate 23798444654 #
Simulator tick rate (ticks/s)
+host_inst_rate 2446370 #
Simulator instruction rate (inst/s)
+host_mem_usage 368136 #
Number of bytes of host memory used
+host_seconds 166.22 #
Real time elapsed on the host
+host_tick_rate 30755543746 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 406624453 #
Number of instructions simulated
+sim_insts 406624458 #
Number of instructions simulated
sim_seconds 5.112051 #
Number of seconds simulated
-sim_ticks 5112051463500 #
Number of ticks simulated
+sim_ticks 5112051446000 #
Number of ticks simulated
system.cpu.dcache.ReadReq_accesses::0 13367989 #
number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13367989 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::0 12053700 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 12053700 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::0 0.098316 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 1314289 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1314289 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_hits::0 12059464 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 12059464 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate::0 0.097885 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 1308525 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1308525 #
number of ReadReq misses
system.cpu.dcache.WriteReq_accesses::0 8403116 #
number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8403116
# number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0 8087096 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 8087096 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::0 0.037607 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 316020 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 316020 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_hits::0 8086815 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 8086815 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_rate::0 0.037641 #
miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 316301 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 316301 #
number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 12.424940 #
Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 12.417813 #
Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
@@ -37,16 +37,16 @@
system.cpu.dcache.demand_avg_miss_latency::1 no_value
# average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total no_value
# average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency no_value
# average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 20140796 #
number of demand (read+write) hits
+system.cpu.dcache.demand_hits::0 20146279 #
number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 #
number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 20140796 #
number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 20146279 #
number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 0 #
number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.074884 #
miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::0 0.074632 #
miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value #
miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value #
miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 1630309 #
number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0 1624826 #
number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 #
number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1630309 #
number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1624826 #
number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 0
# number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::0 0
# mshr miss rate for demand accesses
@@ -56,8 +56,8 @@
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999963 #
Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 511.980804 #
Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.999999 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 511.999375 #
Average occupied blocks per context
system.cpu.dcache.overall_accesses::0 21771105 #
number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 #
number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21771105 #
number of overall (read+write) accesses
@@ -66,16 +66,16 @@
system.cpu.dcache.overall_avg_miss_latency::total no_value
# average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency no_value
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 20140796 #
number of overall hits
+system.cpu.dcache.overall_hits::0 20146279 #
number of overall hits
system.cpu.dcache.overall_hits::1 0 #
number of overall hits
-system.cpu.dcache.overall_hits::total 20140796 #
number of overall hits
+system.cpu.dcache.overall_hits::total 20146279 #
number of overall hits
system.cpu.dcache.overall_miss_latency 0 #
number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.074884 #
miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::0 0.074632 #
miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value #
miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value
# miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 1630309 #
number of overall misses
+system.cpu.dcache.overall_misses::0 1624826 #
number of overall misses
system.cpu.dcache.overall_misses::1 0 #
number of overall misses
-system.cpu.dcache.overall_misses::total 1630309 #
number of overall misses
+system.cpu.dcache.overall_misses::total 1624826 #
number of overall misses
system.cpu.dcache.overall_mshr_hits 0 #
number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 0
# number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::0 0
# mshr miss rate for overall accesses
@@ -84,23 +84,23 @@
system.cpu.dcache.overall_mshr_misses 0 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 1620657 #
number of replacements
-system.cpu.dcache.sampled_refs 1621150 #
Sample count of references to valid blocks.
+system.cpu.dcache.replacements 1622039 #
number of replacements
+system.cpu.dcache.sampled_refs 1622551 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.980804 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 20142691 #
Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 511.999375 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 20148535 #
Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7549500 #
Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 1525412 #
number of writebacks
-system.cpu.dtb_walker_cache.ReadExReq_accesses::1 21821
# number of ReadExReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadExReq_accesses::total 21821
# number of ReadExReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadExReq_hits::1 8119
# number of ReadExReq hits
-system.cpu.dtb_walker_cache.ReadExReq_hits::total 8119
# number of ReadExReq hits
-system.cpu.dtb_walker_cache.ReadExReq_miss_rate::1 0.627927
# miss rate for ReadExReq accesses
-system.cpu.dtb_walker_cache.ReadExReq_misses::1 13702
# number of ReadExReq misses
-system.cpu.dtb_walker_cache.ReadExReq_misses::total 13702
# number of ReadExReq misses
+system.cpu.dcache.writebacks 1526505 #
number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_accesses::1 21821
# number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total 21821
# number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_hits::1 12006
# number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total 12006
# number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.449796
# miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_misses::1 9815
# number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total 9815
# number of ReadReq misses
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_refs 1.289175 #
Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs 1.388452 #
Average number of references to valid blocks.
system.cpu.dtb_walker_cache.blocked::no_mshrs 0
# number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0
# number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
@@ -114,15 +114,15 @@
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total no_value
# average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency no_value
# average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_hits::0 0
# number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::1 8119
# number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 8119
# number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::1 12006
# number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total 12006
# number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_miss_latency 0
# number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value
# miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::1 0.627927
# miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::1 0.449796
# miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total no_value
# miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_misses::0 0
# number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::1 13702
# number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 13702
# number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::1 9815
# number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total 9815
# number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_mshr_hits 0
# number of demand (read+write) MSHR hits
system.cpu.dtb_walker_cache.demand_mshr_miss_latency 0
# number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 no_value
# mshr miss rate for demand accesses
@@ -132,8 +132,8 @@
system.cpu.dtb_walker_cache.fast_writes 0 #
number of fast writes performed
system.cpu.dtb_walker_cache.mshr_cap_events 0
# number of times MSHR cap was activated
system.cpu.dtb_walker_cache.no_allocate_misses 0
# Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.occ_%::1 0.312845 #
Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_blocks::1 5.005513 #
Average occupied blocks per context
+system.cpu.dtb_walker_cache.occ_%::1 0.313148 #
Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_blocks::1 5.010366 #
Average occupied blocks per context
system.cpu.dtb_walker_cache.overall_accesses::0 0
# number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::1 21821
# number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 21821
# number of overall (read+write) accesses
@@ -143,15 +143,15 @@
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency no_value
# average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
system.cpu.dtb_walker_cache.overall_hits::0 0
# number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::1 8119
# number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 8119
# number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::1 12006
# number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total 12006
# number of overall hits
system.cpu.dtb_walker_cache.overall_miss_latency 0
# number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value
# miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::1 0.627927
# miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::1 0.449796
# miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total no_value
# miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_misses::0 0
# number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::1 13702
# number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 13702
# number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::1 9815
# number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total 9815
# number of overall misses
system.cpu.dtb_walker_cache.overall_mshr_hits 0
# number of overall MSHR hits
system.cpu.dtb_walker_cache.overall_mshr_miss_latency 0
# number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 no_value
# mshr miss rate for overall accesses
@@ -160,38 +160,38 @@
system.cpu.dtb_walker_cache.overall_mshr_misses 0
# number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.replacements 7920 #
number of replacements
-system.cpu.dtb_walker_cache.sampled_refs 7926 #
Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.replacements 8629 #
number of replacements
+system.cpu.dtb_walker_cache.sampled_refs 8642 #
Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0
# number of mshr full events for SW prefetching instrutions
-system.cpu.dtb_walker_cache.tagsinuse 5.005513 #
Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs 10218 #
Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5101233174000 #
Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.writebacks 7801 #
number of writebacks
-system.cpu.icache.ReadReq_accesses::0 254189384 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 254189384 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits::0 253396963 #
number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 253396963 #
number of ReadReq hits
+system.cpu.dtb_walker_cache.tagsinuse 5.010366 #
Cycle average of tags in use
+system.cpu.dtb_walker_cache.total_refs 11999 #
Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5100489496500 #
Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.writebacks 2437 #
number of writebacks
+system.cpu.icache.ReadReq_accesses::0 254189385 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 254189385 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_hits::0 253396964 #
number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 253396964 #
number of ReadReq hits
system.cpu.icache.ReadReq_miss_rate::0 0.003117 #
miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::0 792421 #
number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 792421 #
number of ReadReq misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.icache.avg_refs 319.778503 #
Average number of references to valid blocks.
+system.cpu.icache.avg_refs 319.778505 #
Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.icache.cache_copies 0 #
number of cache copies performed
-system.cpu.icache.demand_accesses::0 254189384 #
number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::0 254189385 #
number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1 0 #
number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 254189384 #
number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 254189385 #
number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency::0 0
# average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1 no_value
# average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total no_value
# average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency no_value
# average overall mshr miss latency
-system.cpu.icache.demand_hits::0 253396963 #
number of demand (read+write) hits
+system.cpu.icache.demand_hits::0 253396964 #
number of demand (read+write) hits
system.cpu.icache.demand_hits::1 0 #
number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 253396963 #
number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 253396964 #
number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 0 #
number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate::0 0.003117 #
miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1 no_value #
miss rate for demand accesses
@@ -210,17 +210,17 @@
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.997320 #
Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 510.627884 #
Average occupied blocks per context
-system.cpu.icache.overall_accesses::0 254189384 #
number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::0 254189385 #
number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1 0 #
number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 254189384 #
number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 254189385 #
number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::0 0
# average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1 no_value
# average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total no_value
# average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency no_value
# average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 253396963 #
number of overall hits
+system.cpu.icache.overall_hits::0 253396964 #
number of overall hits
system.cpu.icache.overall_hits::1 0 #
number of overall hits
-system.cpu.icache.overall_hits::total 253396963 #
number of overall hits
+system.cpu.icache.overall_hits::total 253396964 #
number of overall hits
system.cpu.icache.overall_miss_latency 0 #
number of overall miss cycles
system.cpu.icache.overall_miss_rate::0 0.003117 #
miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1 no_value #
miss rate for overall accesses
@@ -240,24 +240,24 @@
system.cpu.icache.sampled_refs 792414 #
Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 510.627884 #
Cycle average of tags in use
-system.cpu.icache.total_refs 253396963 #
Total number of references to valid blocks.
+system.cpu.icache.total_refs 253396964 #
Total number of references to valid blocks.
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