changeset e08035e1a1f6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e08035e1a1f6
description:
ARM: Allow conditional quiesce instructions.
This patch prevents not executed conditional instructions marked as
IsQuiesce from stalling the pipeline indefinitely. If the instruction
is not executed the quiesceSkip psuedoinst is called which schedules a
wakes up call to the fetch stage.
diffstat:
src/arch/arm/isa/insts/m5ops.isa | 6 +++---
src/arch/arm/isa/insts/misc.isa | 20 +++++++++++++-------
src/arch/arm/isa/templates/pred.isa | 32 ++++++++++++++++++++++++++++++++
src/sim/pseudo_inst.cc | 34 ++++++++++++++++++++++++++++++++++
src/sim/pseudo_inst.hh | 1 +
5 files changed, 83 insertions(+), 10 deletions(-)
diffs (190 lines):
diff -r ce34f14c1f43 -r e08035e1a1f6 src/arch/arm/isa/insts/m5ops.isa
--- a/src/arch/arm/isa/insts/m5ops.isa Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/isa/insts/m5ops.isa Thu Mar 17 19:20:20 2011 -0500
@@ -66,7 +66,7 @@
["IsNonSpeculative", "IsQuiesce"])
header_output += BasicDeclare.subst(quiesceIop)
decoder_output += BasicConstructor.subst(quiesceIop)
- exec_output += PredOpExecute.subst(quiesceIop)
+ exec_output += QuiescePredOpExecute.subst(quiesceIop)
quiesceNsCode = '''
#if FULL_SYSTEM
@@ -80,7 +80,7 @@
["IsNonSpeculative", "IsQuiesce"])
header_output += BasicDeclare.subst(quiesceNsIop)
decoder_output += BasicConstructor.subst(quiesceNsIop)
- exec_output += PredOpExecute.subst(quiesceNsIop)
+ exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
quiesceCyclesCode = '''
#if FULL_SYSTEM
@@ -94,7 +94,7 @@
["IsNonSpeculative", "IsQuiesce",
"IsUnverifiable"])
header_output += BasicDeclare.subst(quiesceCyclesIop)
decoder_output += BasicConstructor.subst(quiesceCyclesIop)
- exec_output += PredOpExecute.subst(quiesceCyclesIop)
+ exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
quiesceTimeCode = '''
#if FULL_SYSTEM
diff -r ce34f14c1f43 -r e08035e1a1f6 src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/isa/insts/misc.isa Thu Mar 17 19:20:20 2011 -0500
@@ -491,10 +491,13 @@
wfeCode = '''
#if FULL_SYSTEM
- if (SevMailbox)
+ if (SevMailbox) {
SevMailbox = 0;
- else
+ PseudoInst::quiesceSkip(xc->tcBase());
+ }
+ else {
PseudoInst::quiesce(xc->tcBase());
+ }
#endif
'''
wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
@@ -502,7 +505,7 @@
["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
header_output += BasicDeclare.subst(wfeIop)
decoder_output += BasicConstructor.subst(wfeIop)
- exec_output += PredOpExecute.subst(wfeIop)
+ exec_output += QuiescePredOpExecute.subst(wfeIop)
wfiCode = '''
#if FULL_SYSTEM
@@ -511,22 +514,25 @@
'''
wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
{ "code" : wfiCode, "predicate_test" : predicateTest },
- ["IsNonSpeculative", "IsQuiesce"])
+ ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
header_output += BasicDeclare.subst(wfiIop)
decoder_output += BasicConstructor.subst(wfiIop)
- exec_output += PredOpExecute.subst(wfiIop)
+ exec_output += QuiescePredOpExecute.subst(wfiIop)
sevCode = '''
// Need a way for O3 to not scoreboard these accesses as pipe flushes.
+ SevMailbox = 1;
System *sys = xc->tcBase()->getSystemPtr();
for (int x = 0; x < sys->numContexts(); x++) {
ThreadContext *oc = sys->getThreadContext(x);
- oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+ if (oc != xc->tcBase()) {
+ oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+ }
}
'''
sevIop = InstObjParams("sev", "SevInst", "PredOp", \
{ "code" : sevCode, "predicate_test" : predicateTest },
- ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
+ ["IsNonSpeculative", "IsSquashAfter"])
header_output += BasicDeclare.subst(sevIop)
decoder_output += BasicConstructor.subst(sevIop)
exec_output += PredOpExecute.subst(sevIop)
diff -r ce34f14c1f43 -r e08035e1a1f6 src/arch/arm/isa/templates/pred.isa
--- a/src/arch/arm/isa/templates/pred.isa Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/isa/templates/pred.isa Thu Mar 17 19:20:20 2011 -0500
@@ -170,6 +170,38 @@
}
}};
+def template QuiescePredOpExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord
*traceData) const
+ {
+ Fault fault = NoFault;
+ uint64_t resTemp = 0;
+ resTemp = resTemp;
+ %(op_decl)s;
+ %(op_rd)s;
+
+ if (%(predicate_test)s)
+ {
+ %(code)s;
+ if (fault == NoFault)
+ {
+ %(op_wb)s;
+ }
+ } else {
+ xc->setPredicate(false);
+#if FULL_SYSTEM
+ PseudoInst::quiesceSkip(xc->tcBase());
+#endif
+ }
+
+ if (fault == NoFault && machInst.itstateMask != 0&&
+ (!isMicroop() || isLastMicroop())) {
+ xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+ }
+
+ return fault;
+ }
+}};
+
def template DataDecode {{
if (machInst.opcode4 == 0) {
if (machInst.sField == 0)
diff -r ce34f14c1f43 -r e08035e1a1f6 src/sim/pseudo_inst.cc
--- a/src/sim/pseudo_inst.cc Thu Mar 17 19:20:20 2011 -0500
+++ b/src/sim/pseudo_inst.cc Thu Mar 17 19:20:20 2011 -0500
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -86,6 +98,28 @@
}
void
+quiesceSkip(ThreadContext *tc)
+{
+ BaseCPU *cpu = tc->getCpuPtr();
+
+ if (!cpu->params()->do_quiesce)
+ return;
+
+ EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
+
+ Tick resume = curTick() + 1;
+
+ cpu->reschedule(quiesceEvent, resume, true);
+
+ DPRINTF(Quiesce, "%s: quiesceSkip() until %d\n",
+ cpu->name(), resume);
+
+ tc->suspend();
+ if (tc->getKernelStats())
+ tc->getKernelStats()->quiesce();
+}
+
+void
quiesceNs(ThreadContext *tc, uint64_t ns)
{
BaseCPU *cpu = tc->getCpuPtr();
diff -r ce34f14c1f43 -r e08035e1a1f6 src/sim/pseudo_inst.hh
--- a/src/sim/pseudo_inst.hh Thu Mar 17 19:20:20 2011 -0500
+++ b/src/sim/pseudo_inst.hh Thu Mar 17 19:20:20 2011 -0500
@@ -45,6 +45,7 @@
#if FULL_SYSTEM
void arm(ThreadContext *tc);
void quiesce(ThreadContext *tc);
+void quiesceSkip(ThreadContext *tc);
void quiesceNs(ThreadContext *tc, uint64_t ns);
void quiesceCycles(ThreadContext *tc, uint64_t cycles);
uint64_t quiesceTime(ThreadContext *tc);
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