changeset ed9c6b16e977 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ed9c6b16e977
description:
Automated merge with ssh://h...@repo.m5sim.org/m5
diffstat:
configs/common/Caches.py
| 3 +
configs/common/FSConfig.py
| 11 +-
src/arch/alpha/predecoder.hh
| 6 +
src/arch/arm/insts/branch.hh
| 1 +
src/arch/arm/insts/macromem.cc
| 86 +-
src/arch/arm/insts/macromem.hh
| 21 +
src/arch/arm/insts/mem.hh
| 8 +-
src/arch/arm/intregs.hh
| 2 +
src/arch/arm/isa.cc
| 10 +
src/arch/arm/isa/formats/fp.isa
| 2 +-
src/arch/arm/isa/insts/branch.isa
| 35 +-
src/arch/arm/isa/insts/ldr.isa
| 25 +-
src/arch/arm/isa/insts/m5ops.isa
| 6 +-
src/arch/arm/isa/insts/macromem.isa
| 84 +-
src/arch/arm/isa/insts/mem.isa
| 25 +-
src/arch/arm/isa/insts/misc.isa
| 20 +-
src/arch/arm/isa/insts/str.isa
| 14 +-
src/arch/arm/isa/operands.isa
| 6 +-
src/arch/arm/isa/templates/branch.isa
| 37 +
src/arch/arm/isa/templates/macromem.isa
| 35 +
src/arch/arm/isa/templates/mem.isa
| 24 +-
src/arch/arm/isa/templates/pred.isa
| 32 +
src/arch/arm/linux/process.cc
| 34 +-
src/arch/arm/linux/system.cc
| 24 +
src/arch/arm/linux/system.hh
| 13 +
src/arch/arm/miscregs.hh
| 17 +-
src/arch/arm/predecoder.hh
| 13 +-
src/arch/arm/types.hh
| 13 +
src/arch/mips/predecoder.hh
| 6 +
src/arch/power/predecoder.hh
| 6 +
src/arch/sparc/predecoder.hh
| 7 +
src/arch/x86/predecoder.hh
| 6 +
src/cpu/o3/comm.hh
| 57 +-
src/cpu/o3/commit.hh
| 3 +-
src/cpu/o3/commit_impl.hh
| 28 +-
src/cpu/o3/cpu.cc
| 5 +-
src/cpu/o3/fetch.hh
| 4 +-
src/cpu/o3/fetch_impl.hh
| 15 +-
src/cpu/o3/iew_impl.hh
| 6 +-
src/cpu/o3/lsq_unit_impl.hh
| 4 +-
src/cpu/simple/atomic.cc
| 3 +
src/cpu/simple/timing.cc
| 4 +
src/cpu/static_inst.hh
| 1 +
src/dev/io_device.cc
| 3 +
src/kern/linux/events.cc
| 37 +
src/kern/linux/events.hh
| 27 +
src/mem/cache/BaseCache.py
| 1 +
src/mem/cache/base.cc
| 1 +
src/mem/cache/base.hh
| 5 +
src/mem/cache/cache_impl.hh
| 2 +-
src/sim/pseudo_inst.cc
| 34 +
src/sim/pseudo_inst.hh
| 1 +
src/sim/syscall_emul.cc
| 14 +
src/sim/syscall_emul.hh
| 2 +
tests/SConscript
| 3 +-
tests/configs/inorder-timing.py
| 6 +-
tests/configs/memtest.py
| 1 +
tests/configs/o3-timing-mp.py
| 1 +
tests/configs/o3-timing.py
| 6 +-
tests/configs/pc-simple-atomic.py
| 3 +
tests/configs/pc-simple-timing.py
| 1 +
tests/configs/realview-o3.py
| 99 +
tests/configs/realview-simple-atomic.py
| 1 +
tests/configs/realview-simple-timing.py
| 1 +
tests/configs/simple-atomic-mp.py
| 1 +
tests/configs/simple-timing-mp.py
| 1 +
tests/configs/simple-timing.py
| 6 +-
tests/configs/tsunami-o3-dual.py
| 2 +
tests/configs/tsunami-o3.py
| 2 +
tests/configs/tsunami-simple-atomic-dual.py
| 2 +
tests/configs/tsunami-simple-atomic.py
| 2 +
tests/configs/tsunami-simple-timing-dual.py
| 2 +
tests/configs/tsunami-simple-timing.py
| 2 +
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
| 5 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
| 782 ++--
tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/long/00.gzip/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
| 210 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
| 18 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
| 12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
| 1732 +++++-----
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
| 16 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
| 12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
| 934 ++--
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
| 950 +++++
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr
| 43 +
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
| 16 +
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 750 ++++
tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
| 1 +
tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
| 0
tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
| 7 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
| 787 ++--
tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
| 4 +-
tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
| 7 +-
tests/long/10.mcf/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
| 182 +-
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
| 7 +-
tests/long/20.parser/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
| 782 ++--
tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
| 4 +-
tests/long/20.parser/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
| 7 +-
tests/long/20.parser/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
| 250 +-
tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
| 5 +-
tests/long/30.eon/ref/arm/linux/o3-timing/simout
| 12 +-
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
| 773 ++--
tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/30.eon/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/long/30.eon/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
| 164 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
| 5 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
| 777 ++--
tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
| 194 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
| 5 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
| 803 ++--
tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/long/50.vortex/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
| 236 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
| 5 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
| 792 ++--
tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
| 10 +-
tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
| 202 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
| 5 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/simout
| 12 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
| 778 ++--
tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
| 12 +-
tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
| 36 +-
tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/long/70.twolf/ref/arm/linux/simple-timing/simout
| 12 +-
tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
| 160 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
| 3 +
tests/quick/00.hello/ref/arm/linux/o3-timing/simout
| 10 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
| 746 ++--
tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
| 10 +-
tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
| 34 +-
tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
| 5 +-
tests/quick/00.hello/ref/arm/linux/simple-timing/simout
| 10 +-
tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
| 186 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
| 10 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
| 10 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 358 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
| 2 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
| 0
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
| 10 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
| 8 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 24 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
| 2 +-
175 files changed, 9044 insertions(+), 6417 deletions(-)
diffs (truncated from 21504 to 300 lines):
diff -r b0ecadb07742 -r ed9c6b16e977 configs/common/Caches.py
--- a/configs/common/Caches.py Thu Mar 17 17:08:35 2011 -0700
+++ b/configs/common/Caches.py Thu Mar 17 19:24:37 2011 -0500
@@ -34,6 +34,7 @@
latency = '1ns'
mshrs = 10
tgts_per_mshr = 5
+ is_top_level = True
class L2Cache(BaseCache):
assoc = 8
@@ -49,6 +50,7 @@
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
+ is_top_level = True
class IOCache(BaseCache):
assoc = 8
@@ -58,3 +60,4 @@
size = '1kB'
tgts_per_mshr = 12
forward_snoops = False
+ is_top_level = True
diff -r b0ecadb07742 -r ed9c6b16e977 configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Thu Mar 17 17:08:35 2011 -0700
+++ b/configs/common/FSConfig.py Thu Mar 17 19:24:37 2011 -0500
@@ -201,13 +201,8 @@
self.membus = MemBus(bus_id=1)
self.membus.badaddr_responder.warn_access = "warn"
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
- self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
- self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size =
'128MB'),
- file = disk('ael-arm.ext2'))
self.bridge.side_a = self.iobus.port
self.bridge.side_b = self.membus.port
- self.physmem.port = self.membus.port
- self.diskmem.port = self.membus.port
self.mem_mode = mem_mode
@@ -232,13 +227,19 @@
if bare_metal:
# EOT character on UART will end the simulation
self.realview.uart.end_on_eot = True
+ self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')), zero =
True)
else:
+ self.physmem = PhysicalMemory(range = AddrRange(Addr('128MB')), zero =
True)
+ self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size =
'128MB'),
+ file = disk('ael-arm.ext2'))
+ self.diskmem.port = self.membus.port
self.machine_type = machine_type
self.kernel = binary('vmlinux.arm')
self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0' +
\
' lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000' +
\
' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0'
+ self.physmem.port = self.membus.port
self.realview.attachOnChipIO(self.membus)
self.realview.attachIO(self.iobus)
diff -r b0ecadb07742 -r ed9c6b16e977 src/arch/alpha/predecoder.hh
--- a/src/arch/alpha/predecoder.hh Thu Mar 17 17:08:35 2011 -0700
+++ b/src/arch/alpha/predecoder.hh Thu Mar 17 19:24:37 2011 -0500
@@ -76,6 +76,12 @@
emiIsReady = false;
}
+ void
+ reset(const ExtMachInst &old_emi)
+ {
+ reset();
+ }
+
// Use this to give data to the predecoder. This should be used
// when there is control flow.
void
diff -r b0ecadb07742 -r ed9c6b16e977 src/arch/arm/insts/branch.hh
--- a/src/arch/arm/insts/branch.hh Thu Mar 17 17:08:35 2011 -0700
+++ b/src/arch/arm/insts/branch.hh Thu Mar 17 19:24:37 2011 -0500
@@ -57,6 +57,7 @@
int32_t _imm) :
PredOp(mnem, _machInst, __opClass), imm(_imm)
{}
+
};
// Conditionally Branch to a target computed with an immediate
diff -r b0ecadb07742 -r ed9c6b16e977 src/arch/arm/insts/macromem.cc
--- a/src/arch/arm/insts/macromem.cc Thu Mar 17 17:08:35 2011 -0700
+++ b/src/arch/arm/insts/macromem.cc Thu Mar 17 19:24:37 2011 -0500
@@ -58,8 +58,13 @@
{
uint32_t regs = reglist;
uint32_t ones = number_of_ones(reglist);
- // Remember that writeback adds a uop
- numMicroops = ones + (writeback ? 1 : 0) + 1;
+ // Remember that writeback adds a uop or two and the temp register adds one
+ numMicroops = ones + (writeback ? (load ? 2 : 1) : 0) + 1;
+
+ // It's technically legal to do a lot of nothing
+ if (!ones)
+ numMicroops = 1;
+
microOps = new StaticInstPtr[numMicroops];
uint32_t addr = 0;
@@ -70,28 +75,13 @@
addr += 4;
StaticInstPtr *uop = microOps;
- StaticInstPtr wbUop;
- if (writeback) {
- if (up) {
- wbUop = new MicroAddiUop(machInst, rn, rn, ones * 4);
- } else {
- wbUop = new MicroSubiUop(machInst, rn, rn, ones * 4);
- }
- }
// Add 0 to Rn and stick it in ureg0.
// This is equivalent to a move.
*uop = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
- // Write back at the start for loads. This covers the ldm exception return
- // case where the base needs to be written in the old mode. Stores may need
- // the original value of the base, but they don't change mode and can
- // write back at the end like before.
- if (load && writeback) {
- *++uop = wbUop;
- }
-
unsigned reg = 0;
+ unsigned regIdx = 0;
bool force_user = user & !bits(reglist, 15);
bool exception_ret = user & bits(reglist, 15);
@@ -101,19 +91,28 @@
reg++;
replaceBits(regs, reg, 0);
- unsigned regIdx = reg;
+ regIdx = reg;
if (force_user) {
regIdx = intRegInMode(MODE_USER, regIdx);
}
if (load) {
- if (reg == INTREG_PC && exception_ret) {
- // This must be the exception return form of ldm.
- *++uop = new MicroLdrRetUop(machInst, regIdx,
- INTREG_UREG0, up, addr);
+ if (writeback && i == ones - 1) {
+ // If it's a writeback and this is the last register
+ // do the load into a temporary register which we'll move
+ // into the final one later
+ *++uop = new MicroLdrUop(machInst, INTREG_UREG1, INTREG_UREG0,
+ up, addr);
} else {
- *++uop = new MicroLdrUop(machInst, regIdx,
- INTREG_UREG0, up, addr);
+ // Otherwise just do it normally
+ if (reg == INTREG_PC && exception_ret) {
+ // This must be the exception return form of ldm.
+ *++uop = new MicroLdrRetUop(machInst, regIdx,
+ INTREG_UREG0, up, addr);
+ } else {
+ *++uop = new MicroLdrUop(machInst, regIdx,
+ INTREG_UREG0, up, addr);
+ }
}
} else {
*++uop = new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr);
@@ -125,8 +124,32 @@
addr -= 4;
}
- if (!load && writeback) {
- *++uop = wbUop;
+ if (writeback && ones) {
+ // put the register update after we're done all loading
+ if (up)
+ *++uop = new MicroAddiUop(machInst, rn, rn, ones * 4);
+ else
+ *++uop = new MicroSubiUop(machInst, rn, rn, ones * 4);
+
+ // If this was a load move the last temporary value into place
+ // this way we can't take an exception after we update the base
+ // register.
+ if (load && reg == INTREG_PC && exception_ret) {
+ *++uop = new MicroUopRegMovRet(machInst, 0, INTREG_UREG1);
+ warn("creating instruction with exception return at curTick:%d\n",
+ curTick());
+ } else if (load) {
+ *++uop = new MicroUopRegMov(machInst, regIdx, INTREG_UREG1);
+ if (reg == INTREG_PC) {
+ (*uop)->setFlag(StaticInstBase::IsControl);
+ (*uop)->setFlag(StaticInstBase::IsCondControl);
+ (*uop)->setFlag(StaticInstBase::IsIndirectControl);
+ // This is created as a RAS POP
+ if (rn == INTREG_SP)
+ (*uop)->setFlag(StaticInstBase::IsReturn);
+
+ }
+ }
}
(*uop)->setLastMicroop();
@@ -896,6 +919,15 @@
}
std::string
+MicroSetPCCPSR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ ss << "[PC,CPSR]";
+ return ss.str();
+}
+
+std::string
MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
diff -r b0ecadb07742 -r ed9c6b16e977 src/arch/arm/insts/macromem.hh
--- a/src/arch/arm/insts/macromem.hh Thu Mar 17 17:08:35 2011 -0700
+++ b/src/arch/arm/insts/macromem.hh Thu Mar 17 19:24:37 2011 -0500
@@ -134,6 +134,27 @@
{
}
};
+
+/**
+ * Microops of the form
+ * PC = IntRegA
+ * CPSR = IntRegB
+ */
+class MicroSetPCCPSR : public MicroOp
+{
+ protected:
+ IntRegIndex ura, urb, urc;
+
+ MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+ IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
+ : MicroOp(mnem, machInst, __opClass),
+ ura(_ura), urb(_urb), urc(_urc)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
/**
* Microops of the form IntRegA = IntRegB
*/
diff -r b0ecadb07742 -r ed9c6b16e977 src/arch/arm/insts/mem.hh
--- a/src/arch/arm/insts/mem.hh Thu Mar 17 17:08:35 2011 -0700
+++ b/src/arch/arm/insts/mem.hh Thu Mar 17 19:24:37 2011 -0500
@@ -97,14 +97,18 @@
IntRegIndex base;
AddrMode mode;
bool wb;
- static const unsigned numMicroops = 2;
+ IntRegIndex ura, urb, urc;
+ static const unsigned numMicroops = 3;
StaticInstPtr *uops;
RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _base, AddrMode _mode, bool _wb)
: MightBeMicro(mnem, _machInst, __opClass),
- base(_base), mode(_mode), wb(_wb), uops(NULL)
+ base(_base), mode(_mode), wb(_wb),
+ ura(INTREG_UREG0), urb(INTREG_UREG1),
+ urc(INTREG_UREG2),
+ uops(NULL)
{}
virtual
diff -r b0ecadb07742 -r ed9c6b16e977 src/arch/arm/intregs.hh
--- a/src/arch/arm/intregs.hh Thu Mar 17 17:08:35 2011 -0700
+++ b/src/arch/arm/intregs.hh Thu Mar 17 19:24:37 2011 -0500
@@ -110,6 +110,8 @@
INTREG_ZERO, // Dummy zero reg since there has to be one.
INTREG_UREG0,
+ INTREG_UREG1,
+ INTREG_UREG2,
INTREG_CONDCODES,
INTREG_FPCONDCODES,
diff -r b0ecadb07742 -r ed9c6b16e977 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Thu Mar 17 17:08:35 2011 -0700
+++ b/src/arch/arm/isa.cc Thu Mar 17 19:24:37 2011 -0500
@@ -143,6 +143,16 @@
miscRegs[MISCREG_CPACR] = 0;
miscRegs[MISCREG_FPSID] = 0x410430A0;
+
+ // See section B4.1.84 of ARM ARM
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