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Review request for Default. Summary ------- Ruby: Convert AccessModeType to RubyAccessMode This patch converts AccessModeType to RubyAccessMode so that both the protocol dependent and independent code uses the same access mode. Diffs ----- src/cpu/testers/rubytest/Check.hh 9a6a02a235f1 src/cpu/testers/rubytest/Check.cc 9a6a02a235f1 src/mem/protocol/MESI_CMP_directory-msg.sm 9a6a02a235f1 src/mem/protocol/MOESI_CMP_directory-msg.sm 9a6a02a235f1 src/mem/protocol/MOESI_CMP_token-L1cache.sm 9a6a02a235f1 src/mem/protocol/MOESI_CMP_token-dir.sm 9a6a02a235f1 src/mem/protocol/MOESI_CMP_token-msg.sm 9a6a02a235f1 src/mem/protocol/RubySlicc_Exports.sm 9a6a02a235f1 src/mem/protocol/RubySlicc_Types.sm 9a6a02a235f1 src/mem/ruby/profiler/AccessTraceForAddress.hh 9a6a02a235f1 src/mem/ruby/profiler/AccessTraceForAddress.cc 9a6a02a235f1 src/mem/ruby/profiler/AddressProfiler.hh 9a6a02a235f1 src/mem/ruby/profiler/AddressProfiler.cc 9a6a02a235f1 src/mem/ruby/profiler/CacheProfiler.hh 9a6a02a235f1 src/mem/ruby/profiler/CacheProfiler.cc 9a6a02a235f1 src/mem/ruby/profiler/Profiler.hh 9a6a02a235f1 src/mem/ruby/slicc_interface/RubyRequest.hh 9a6a02a235f1 src/mem/ruby/system/CacheMemory.hh 9a6a02a235f1 src/mem/ruby/system/CacheMemory.cc 9a6a02a235f1 src/mem/ruby/system/Sequencer.hh 9a6a02a235f1 src/mem/ruby/system/Sequencer.cc 9a6a02a235f1 Diff: http://reviews.m5sim.org/r/601/diff Testing ------- Thanks, Nilay _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
