changeset 19444b1f092c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=19444b1f092c
description:
        This patch adds the network tester for simple and garnet networks.
        The tester code is in testers/networktest.
        The tester can be invoked by configs/example/ruby_network_test.py.
        A dummy coherence protocol called Network_test is also addded for 
network-only simulations and testing. The protocol takes in messages from the 
tester and just pushes them into the network in the appropriate vnet, without 
storing any state.

diffstat:

 build_opts/ALPHA_SE_Network_test                                  |    5 +
 configs/example/ruby_network_test.py                              |  131 +++
 configs/ruby/Network_test.py                                      |  129 +++
 src/cpu/testers/networktest/NetworkTest.py                        |   42 +
 src/cpu/testers/networktest/SConscript                            |   37 +
 src/cpu/testers/networktest/networktest.cc                        |  333 
++++++++++
 src/cpu/testers/networktest/networktest.hh                        |  158 ++++
 src/mem/protocol/Network_test-cache.sm                            |  218 ++++++
 src/mem/protocol/Network_test-dir.sm                              |  136 ++++
 src/mem/protocol/Network_test-msg.sm                              |   77 ++
 src/mem/protocol/Network_test.slicc                               |    4 +
 src/mem/protocol/SConsopts                                        |    1 +
 src/mem/ruby/network/garnet/BaseGarnetNetwork.cc                  |    1 -
 src/mem/ruby/network/garnet/BaseGarnetNetwork.hh                  |    3 +-
 src/mem/ruby/network/garnet/BaseGarnetNetwork.py                  |    1 -
 src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc     |   14 +-
 src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc  |    9 +-
 src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc |    8 +-
 src/mem/ruby/system/Sequencer.cc                                  |    8 +-
 src/mem/ruby/system/Sequencer.hh                                  |    2 +
 src/mem/ruby/system/Sequencer.py                                  |    1 +
 21 files changed, 1294 insertions(+), 24 deletions(-)

diffs (truncated from 1482 to 300 lines):

diff -r c1c6f36e118e -r 19444b1f092c build_opts/ALPHA_SE_Network_test
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/build_opts/ALPHA_SE_Network_test  Mon Mar 21 22:51:58 2011 -0400
@@ -0,0 +1,5 @@
+FULL_SYSTEM = 0
+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'Network_test'
+RUBY = True
diff -r c1c6f36e118e -r 19444b1f092c configs/example/ruby_network_test.py
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/configs/example/ruby_network_test.py      Mon Mar 21 22:51:58 2011 -0400
@@ -0,0 +1,131 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+#          Tushar Krishna
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
+addToPath('../common')
+addToPath('../ruby')
+import Ruby
+
+if buildEnv['FULL_SYSTEM']:
+    panic("This script requires system-emulation mode (*_SE).")
+
+# Get paths we might need.  It's expected this file is in m5/configs/example.
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
+
+parser = optparse.OptionParser()
+
+parser.add_option("--synthetic", type="int", default=0,
+                  help="Synthetic Traffic type. 0 = Uniform Random,\
+                        1 = Tornado, 2 = Bit Complement")
+
+parser.add_option("-i", "--injectionrate", type="float", default=0.1,
+                  metavar="I",
+                  help="Injection rate in packets per cycle per node. \
+                        Takes decimal value between 0 to 1 (eg. 0.225). \
+                        Number of digits after 0 depends upon --precision.")
+
+parser.add_option("--precision", type="int", default=3,
+                  help="Number of digits of precision after decimal point\
+                        for injection rate")
+
+parser.add_option("--fixed-pkts", action="store_true",
+                  help="Network_test: send only -p number of packets")
+
+parser.add_option("-p", "--maxpackets", type="int", default=1,
+                  metavar="P",
+                  help="Stop after Packets (works only with --fixed-pkts")
+
+#
+# Add the ruby specific and protocol specific options
+#
+Ruby.define_options(parser)
+
+execfile(os.path.join(config_root, "common", "Options.py"))
+
+(options, args) = parser.parse_args()
+
+if args:
+     print "Error: script doesn't take any positional arguments"
+     sys.exit(1)
+
+block_size = 64
+
+if options.num_cpus > block_size:
+     print "Error: Number of cores %d limited to %d because of false sharing" \
+           % (options.num_cpus, block_size)
+     sys.exit(1)
+
+cpus = [ NetworkTest(fixed_pkts=options.fixed_pkts, \
+                     max_packets=options.maxpackets, \
+                     traffic_type=options.synthetic, \
+                     inj_rate=options.injectionrate, \
+                     precision=options.precision, \
+                     num_memories=options.num_dirs) \
+         for i in xrange(options.num_cpus) ]
+
+# create the desired simulated system
+system = System(cpu = cpus,
+                physmem = PhysicalMemory())
+
+system.ruby = Ruby.create_system(options, system)
+
+i = 0
+for ruby_port in system.ruby.cpu_ruby_ports:
+     #
+     # Tie the cpu test ports to the ruby cpu port
+     #
+     cpus[i].test = ruby_port.port
+     ruby_port.access_phys_mem = False
+
+     i += 1
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( system = system )
+root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')
+
+# instantiate configuration
+m5.instantiate()
+
+# simulate until program terminates
+exit_event = m5.simulate(options.maxtick)
+
+print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
diff -r c1c6f36e118e -r 19444b1f092c configs/ruby/Network_test.py
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/configs/ruby/Network_test.py      Mon Mar 21 22:51:58 2011 -0400
@@ -0,0 +1,129 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+
+#
+# Note: the cache latency is only used by the sequencer on fast path hits
+#
+class Cache(RubyCache):
+    latency = 3
+
+def define_options(parser):
+    return
+
+def create_system(options, system, piobus, dma_devices):
+    
+    if buildEnv['PROTOCOL'] != 'Network_test':
+        panic("This script requires the Network_test protocol to be built.")
+
+    cpu_sequencers = []
+
+    #
+    # The Garnet tester protocol does not support fs nor dma
+    #
+    if buildEnv['FULL_SYSTEM']:
+        panic("This script requires system-emulation mode (*_SE).")
+    assert(piobus == None)
+    assert(dma_devices == [])
+    
+    #
+    # The ruby network creation expects the list of nodes in the system to be
+    # consistent with the NetDest list.  Therefore the l1 controller nodes 
must be
+    # listed before the directory nodes and directory nodes before dma nodes, 
etc.
+    #
+    l1_cntrl_nodes = []
+    dir_cntrl_nodes = []
+
+    #
+    # Must create the individual controllers before the network to ensure the
+    # controller constructors are called before the network constructor
+    #
+
+    for i in xrange(options.num_cpus):
+        #
+        # First create the Ruby objects associated with this cpu
+        # Only one cache exists for this protocol, so by default use the L1D
+        # config parameters.
+        #
+        cache = Cache(size = options.l1d_size,
+                      assoc = options.l1d_assoc)
+
+        #
+        # Only one unified L1 cache exists.  Can cache instructions and data.
+        #
+        cpu_seq = RubySequencer(icache = cache,
+                                dcache = cache,
+                                physMemPort = system.physmem.port,
+                                physmem = system.physmem,
+                                using_network_tester = True)
+
+        if piobus != None:
+            cpu_seq.pio_port = piobus.port
+
+        l1_cntrl = L1Cache_Controller(version = i,
+                                      sequencer = cpu_seq,
+                                      cacheMemory = cache)
+
+        exec("system.l1_cntrl%d = l1_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(cpu_seq)
+        l1_cntrl_nodes.append(l1_cntrl)
+
+    phys_mem_size = long(system.physmem.range.second) - \
+                      long(system.physmem.range.first) + 1
+    mem_module_size = phys_mem_size / options.num_dirs
+
+    for i in xrange(options.num_dirs):
+        #
+        # Create the Ruby objects associated with the directory controller
+        #
+
+        mem_cntrl = RubyMemoryControl(version = i)
+
+        dir_size = MemorySize('0B')
+        dir_size.value = mem_module_size
+
+        dir_cntrl = Directory_Controller(version = i,
+                                         directory = \
+                                         RubyDirectoryMemory(version = i,
+                                                             size = dir_size),
+                                         memBuffer = mem_cntrl)
+
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
+        dir_cntrl_nodes.append(dir_cntrl)
+
+    all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes
+
+    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
diff -r c1c6f36e118e -r 19444b1f092c src/cpu/testers/networktest/NetworkTest.py
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/src/cpu/testers/networktest/NetworkTest.py        Mon Mar 21 22:51:58 
2011 -0400
@@ -0,0 +1,42 @@
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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