Hi Lisa and Nilay,
Thanks for the response. Following is the tip of my repochangeset: 8174:e21f6e70169e tag: tip user: Nilay Vaish<ni...@cs.wisc.edu> date: Tue Mar 22 06:41:54 2011 -0500 summary: Ruby: Remove CacheMsg class from SLICCSo this is after Nilay's patch for CacheMsg. And yes it did not tun for 10-15 mins, died immediately. The architecture should not matter for random_tester. I am not sure then why its breaking. Seems like something broken.
Thanks Arka On 03/22/2011 08:49 PM, Lisa Hsu wrote:
Hi Arka, My repo it not the current tip, but the tip is Nilay's push removing CacheMsg, so it's pretty close. I've been running X86_SE_MESI_CMP_directory with the random tester for maybe 10 or 15 minutes now, and it hasn't died. Since yours died "immediately", I would assume that I won't be able to reproduce. What's your tip, is it last night's pushes? Lisa On Tue, Mar 22, 2011 at 6:06 PM, Nilay<ni...@cs.wisc.edu> wrote:On Tue, March 22, 2011 6:28 pm, Arkaprava Basu wrote:Hi, I just updated a clean gem5 repo, compiled MESI_CMP_directory and tried to run ruby random tester but it immediately failed as follows. Can any body reproduce this? Thanks ArkaALPHA is working fine for 10000 loads with 4 processors. Since your testing with ruby random tester, would the processor architecture even come in to play? -- Nilay _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev_______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
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