changeset f789b9aac5f4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f789b9aac5f4
description:
mips: cleanup ISA-specific code
***
(1): get rid of expandForMT function
MIPS is the only ISA that cares about having a piece of ISA state
integrate
multiple threads so add constants for MIPS and relieve the other ISAs
from having
to define this. Also, InOrder was the only core that was actively
calling
this function
* * *
(2): get rid of corespecific type
The CoreSpecific type was used as a proxy to pass in HW specific params
to
a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes
sense
to not force every other ISA to use CoreSpecific as well use a special
reset function to set it. That probably should go in a PowerOn reset
fault
anyway.
diffstat:
src/arch/alpha/isa.hh | 8 -----
src/arch/alpha/types.hh | 5 ---
src/arch/arm/types.hh | 4 --
src/arch/mips/isa.cc | 67 ++++++++++++++++++++----------------------------
src/arch/mips/isa.hh | 15 +++++-----
src/arch/mips/types.hh | 30 ++++++++++++++++-----
src/arch/power/types.hh | 4 --
src/arch/sparc/types.hh | 5 ---
src/arch/x86/types.hh | 3 --
src/cpu/BaseCPU.py | 56 ----------------------------------------
src/cpu/base.hh | 2 -
src/cpu/inorder/cpu.cc | 13 ---------
src/cpu/inorder/cpu.hh | 3 --
13 files changed, 57 insertions(+), 158 deletions(-)
diffs (truncated from 424 to 300 lines):
diff -r d8587c913ccf -r f789b9aac5f4 src/arch/alpha/isa.hh
--- a/src/arch/alpha/isa.hh Fri Mar 25 10:13:50 2011 -0700
+++ b/src/arch/alpha/isa.hh Sat Mar 26 09:23:52 2011 -0400
@@ -90,14 +90,6 @@
void unserialize(EventManager *em, Checkpoint *cp,
const std::string §ion);
- void reset(std::string core_name, ThreadID num_threads,
- unsigned num_vpes, BaseCPU *_cpu)
- { }
-
-
- void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
- { }
-
int
flattenIntIndex(int reg)
{
diff -r d8587c913ccf -r f789b9aac5f4 src/arch/alpha/types.hh
--- a/src/arch/alpha/types.hh Fri Mar 25 10:13:50 2011 -0700
+++ b/src/arch/alpha/types.hh Sat Mar 26 09:23:52 2011 -0400
@@ -51,11 +51,6 @@
ITOUCH_ANNOTE = 0xffffffff,
};
-struct CoreSpecific
-{
- int core_type;
-};
-
} // namespace AlphaISA
#endif // __ARCH_ALPHA_TYPES_HH__
diff -r d8587c913ccf -r f789b9aac5f4 src/arch/arm/types.hh
--- a/src/arch/arm/types.hh Fri Mar 25 10:13:50 2011 -0700
+++ b/src/arch/arm/types.hh Sat Mar 26 09:23:52 2011 -0400
@@ -497,10 +497,6 @@
}
}
- struct CoreSpecific {
- // Empty for now on the ARM
- };
-
} // namespace ArmISA
namespace __hash_namespace {
diff -r d8587c913ccf -r f789b9aac5f4 src/arch/mips/isa.cc
--- a/src/arch/mips/isa.cc Fri Mar 25 10:13:50 2011 -0700
+++ b/src/arch/mips/isa.cc Sat Mar 26 09:23:52 2011 -0400
@@ -86,14 +86,11 @@
"LLFlag"
};
-ISA::ISA()
+ISA::ISA(uint8_t num_threads, uint8_t num_vpes)
{
- init();
-}
+ numThreads = num_threads;
+ numVpes = num_vpes;
-void
-ISA::init()
-{
miscRegFile.resize(NumMiscRegs);
bankType.resize(NumMiscRegs);
@@ -107,21 +104,7 @@
for (int i = 0; i < NumMiscRegs; i++) {
miscRegFile_WriteMask[i].push_back(0);
}
- clear(0);
-}
-void
-ISA::clear(unsigned tid_or_vpn)
-{
- for(int i = 0; i < NumMiscRegs; i++) {
- miscRegFile[i][tid_or_vpn] = 0;
- miscRegFile_WriteMask[i][tid_or_vpn] = (long unsigned int)(-1);
- }
-}
-
-void
-ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
-{
// Initialize all Per-VPE regs
uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
@@ -134,8 +117,8 @@
};
uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
for (int i = 0; i < num_vpe_regs; i++) {
- if (num_vpes > 1) {
- miscRegFile[per_vpe_regs[i]].resize(num_vpes);
+ if (numVpes > 1) {
+ miscRegFile[per_vpe_regs[i]].resize(numVpes);
}
bankType[per_vpe_regs[i]] = perVirtProcessor;
}
@@ -151,28 +134,34 @@
uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
for (int i = 0; i < num_tc_regs; i++) {
- miscRegFile[per_tc_regs[i]].resize(num_threads);
+ miscRegFile[per_tc_regs[i]].resize(numThreads);
bankType[per_tc_regs[i]] = perThreadContext;
}
-
- if (num_vpes > 1) {
- for (int i=1; i < num_vpes; i++) {
- clear(i);
- }
- }
-
+ clear();
}
-//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
void
-ISA::reset(std::string core_name, ThreadID num_threads,
- unsigned num_vpes, BaseCPU *cpu)
+ISA::clear()
+{
+ for(int i = 0; i < NumMiscRegs; i++) {
+ for (int j = 0; j < miscRegFile[i].size(); j++)
+ miscRegFile[i][j] = 0;
+
+ for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
+ miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
+ }
+}
+
+
+void
+ISA::configCP()
{
DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
- num_threads, num_vpes);
+ numThreads, numVpes);
- MipsISA::CoreSpecific &cp = cpu->coreParams;
+ CoreSpecific cp;
+ panic("CP state must be set before the following code is used");
// Do Default CP0 initialization HERE
@@ -350,8 +339,8 @@
// MVPConf0
MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
mvpConf0.tca = 1;
- mvpConf0.pvpe = num_vpes - 1;
- mvpConf0.ptc = num_threads - 1;
+ mvpConf0.pvpe = numVpes - 1;
+ mvpConf0.ptc = numThreads - 1;
setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
// VPEConf0
@@ -360,7 +349,7 @@
setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
// TCBind
- for (ThreadID tid = 0; tid < num_threads; tid++) {
+ for (ThreadID tid = 0; tid < numThreads; tid++) {
TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
tcBind.curTC = tid;
setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
@@ -377,7 +366,7 @@
setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
// Set Dynamically Allocatable bit to 1 for all other threads
- for (ThreadID tid = 1; tid < num_threads; tid++) {
+ for (ThreadID tid = 1; tid < numThreads; tid++) {
tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
tcStatus.da = 1;
setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
diff -r d8587c913ccf -r f789b9aac5f4 src/arch/mips/isa.hh
--- a/src/arch/mips/isa.hh Fri Mar 25 10:13:50 2011 -0700
+++ b/src/arch/mips/isa.hh Sat Mar 26 09:23:52 2011 -0400
@@ -54,6 +54,10 @@
typedef ISA CP0;
protected:
+ // Number of threads and vpes an individual ISA state can handle
+ uint8_t numThreads;
+ uint8_t numVpes;
+
enum BankType {
perProcessor,
perThreadContext,
@@ -65,16 +69,11 @@
std::vector<BankType> bankType;
public:
- ISA();
+ ISA(uint8_t num_threads = 1, uint8_t num_vpes = 1);
- void init();
+ void clear();
- void clear(unsigned tid_or_vpn = 0);
-
- void reset(std::string core_name, ThreadID num_threads,
- unsigned num_vpes, BaseCPU *cpu);
-
- void expandForMultithreading(ThreadID num_threads, unsigned num_vpes);
+ void configCP();
unsigned getVPENum(ThreadID tid);
diff -r d8587c913ccf -r f789b9aac5f4 src/arch/mips/types.hh
--- a/src/arch/mips/types.hh Fri Mar 25 10:13:50 2011 -0700
+++ b/src/arch/mips/types.hh Sat Mar 26 09:23:52 2011 -0400
@@ -77,13 +77,28 @@
};
struct CoreSpecific {
- /* Note: It looks like it will be better to allow simulator users
- to specify the values of individual variables instead of requiring
- users to define the values of entire registers
- Especially since a lot of these variables can be created from other
- user parameters (cache descriptions)
- -jpp
- */
+ CoreSpecific()
+ : CP0_IntCtl_IPTI(0), CP0_IntCtl_IPPCI(0), CP0_SrsCtl_HSS(0),
+ CP0_PRId_CompanyOptions(0), CP0_PRId_CompanyID(0),
+ CP0_PRId_ProcessorID(0), CP0_PRId_Revision(0),
+ CP0_EBase_CPUNum(0), CP0_Config_BE(0), CP0_Config_AT(0),
+ CP0_Config_AR(0), CP0_Config_MT(0), CP0_Config_VI(0),
+ CP0_Config1_M(0), CP0_Config1_MMU(0), CP0_Config1_IS(0),
+ CP0_Config1_IL(0), CP0_Config1_IA(0), CP0_Config1_DS(0),
+ CP0_Config1_DL(0), CP0_Config1_DA(0), CP0_Config1_C2(false),
+ CP0_Config1_MD(false), CP0_Config1_PC(false), CP0_Config1_WR(false),
+ CP0_Config1_CA(false), CP0_Config1_EP(false), CP0_Config1_FP(false),
+ CP0_Config2_M(false), CP0_Config2_TU(0), CP0_Config2_TS(0),
+ CP0_Config2_TL(0), CP0_Config2_TA(0), CP0_Config2_SU(0),
+ CP0_Config2_SS(0), CP0_Config2_SL(0), CP0_Config2_SA(0),
+ CP0_Config3_M(false), CP0_Config3_DSPP(false),
CP0_Config3_LPA(false),
+ CP0_Config3_VEIC(false), CP0_Config3_VInt(false),
+ CP0_Config3_SP(false), CP0_Config3_MT(false), CP0_Config3_SM(false),
+ CP0_Config3_TL(false), CP0_WatchHi_M(false), CP0_PerfCtr_M(false),
+ CP0_PerfCtr_W(false), CP0_PRId(0), CP0_Config(0), CP0_Config1(0),
+ CP0_Config2(0), CP0_Config3(0)
+ { }
+
// MIPS CP0 State - First individual variables
// Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM,
// Volume III (PRA)
@@ -149,5 +164,4 @@
};
} // namespace MipsISA
-
#endif
diff -r d8587c913ccf -r f789b9aac5f4 src/arch/power/types.hh
--- a/src/arch/power/types.hh Fri Mar 25 10:13:50 2011 -0700
+++ b/src/arch/power/types.hh Sat Mar 26 09:23:52 2011 -0400
@@ -87,10 +87,6 @@
// typedef int RegContextParam;
// typedef int RegContextVal;
-struct CoreSpecific {
-};
-
-} // PowerISA namspace
namespace __hash_namespace {
diff -r d8587c913ccf -r f789b9aac5f4 src/arch/sparc/types.hh
--- a/src/arch/sparc/types.hh Fri Mar 25 10:13:50 2011 -0700
+++ b/src/arch/sparc/types.hh Sat Mar 26 09:23:52 2011 -0400
@@ -45,11 +45,6 @@
typedef Twin64_t LargestRead;
-struct CoreSpecific
-{
- int core_type;
-};
-
}
#endif
diff -r d8587c913ccf -r f789b9aac5f4 src/arch/x86/types.hh
--- a/src/arch/x86/types.hh Fri Mar 25 10:13:50 2011 -0700
+++ b/src/arch/x86/types.hh Sat Mar 26 09:23:52 2011 -0400
@@ -278,9 +278,6 @@
}
};
- struct CoreSpecific {
- int core_type;
- };
};
namespace __hash_namespace {
diff -r d8587c913ccf -r f789b9aac5f4 src/cpu/BaseCPU.py
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