Hi Steve, Oops. It was such a small change in configuration, I didn't think about rerunning the regression tester, but now thinking about it, yes it could impact the results. The cache indexing functions were not using the right bits before this change.
I can go ahead and update the stats tonight. However, let me know if it is more convenient for you to update them yourself. Brad > -----Original Message----- > From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On > Behalf Of Steve Reinhardt > Sent: Saturday, March 26, 2011 6:20 AM > To: M5 Developer List > Subject: Re: [m5-dev] changeset in m5: ruby: fixed cache index setting > > Hi Brad, > > Would you expect this to change the results for the ruby regressions > slightly? The regressions passed last night because the tests didn't > actually get rerun (since scons doesn't see the config file as a > dependency), but I'm seeing some failures in the tip on tests I'm > running and I suspect it's due to this change. > > Steve > > On Fri, Mar 25, 2011 at 10:15 AM, Brad Beckmann <brad.beckm...@amd.com> > wrote: > > changeset d8587c913ccf in /z/repo/m5 > > details: http://repo.m5sim.org/m5?cmd=changeset;node=d8587c913ccf > > description: > > ruby: fixed cache index setting > > > > diffstat: > > > > configs/ruby/MESI_CMP_directory.py | 17 +++++++++++------ > > configs/ruby/MI_example.py | 4 +++- > > configs/ruby/MOESI_CMP_directory.py | 17 +++++++++++------ > > configs/ruby/MOESI_CMP_token.py | 15 +++++++++------ > > configs/ruby/MOESI_hammer.py | 10 +++++++--- > > 5 files changed, 41 insertions(+), 22 deletions(-) > > > > diffs (207 lines): > > > > diff -r bbab80b639cb -r d8587c913ccf > configs/ruby/MESI_CMP_directory.py > > --- a/configs/ruby/MESI_CMP_directory.py Fri Mar 25 00:46:14 > 2011 -0400 > > +++ b/configs/ruby/MESI_CMP_directory.py Fri Mar 25 10:13:50 > 2011 -0700 > > @@ -68,15 +68,19 @@ > > # Must create the individual controllers before the network to > ensure the > > # controller constructors are called before the network > constructor > > # > > + l2_bits = int(math.log(options.num_l2caches, 2)) > > + block_size_bits = int(math.log(options.cacheline_size, 2)) > > > > for i in xrange(options.num_cpus): > > # > > # First create the Ruby objects associated with this cpu > > # > > l1i_cache = L1Cache(size = options.l1i_size, > > - assoc = options.l1i_assoc) > > + assoc = options.l1i_assoc, > > + start_index_bit = block_size_bits) > > l1d_cache = L1Cache(size = options.l1d_size, > > - assoc = options.l1d_assoc) > > + assoc = options.l1d_assoc, > > + start_index_bit = block_size_bits) > > > > cpu_seq = RubySequencer(version = i, > > icache = l1i_cache, > > @@ -91,9 +95,7 @@ > > sequencer = cpu_seq, > > L1IcacheMemory = l1i_cache, > > L1DcacheMemory = l1d_cache, > > - l2_select_num_bits = \ > > - > math.log(options.num_l2caches, > > - 2)) > > + l2_select_num_bits = l2_bits) > > > > exec("system.l1_cntrl%d = l1_cntrl" % i) > > > > @@ -103,12 +105,15 @@ > > cpu_sequencers.append(cpu_seq) > > l1_cntrl_nodes.append(l1_cntrl) > > > > + l2_index_start = block_size_bits + l2_bits > > + > > for i in xrange(options.num_l2caches): > > # > > # First create the Ruby objects associated with this cpu > > # > > l2_cache = L2Cache(size = options.l2_size, > > - assoc = options.l2_assoc) > > + assoc = options.l2_assoc, > > + start_index_bit = l2_index_start) > > > > l2_cntrl = L2Cache_Controller(version = i, > > L2cacheMemory = l2_cache) > > diff -r bbab80b639cb -r d8587c913ccf configs/ruby/MI_example.py > > --- a/configs/ruby/MI_example.py Fri Mar 25 00:46:14 2011 - > 0400 > > +++ b/configs/ruby/MI_example.py Fri Mar 25 10:13:50 2011 - > 0700 > > @@ -60,6 +60,7 @@ > > # Must create the individual controllers before the network to > ensure the > > # controller constructors are called before the network > constructor > > # > > + block_size_bits = int(math.log(options.cacheline_size, 2)) > > > > for i in xrange(options.num_cpus): > > # > > @@ -68,7 +69,8 @@ > > # config parameters. > > # > > cache = Cache(size = options.l1d_size, > > - assoc = options.l1d_assoc) > > + assoc = options.l1d_assoc, > > + start_index_bit = block_size_bits) > > > > # > > # Only one unified L1 cache exists. Can cache instructions > and data. > > diff -r bbab80b639cb -r d8587c913ccf > configs/ruby/MOESI_CMP_directory.py > > --- a/configs/ruby/MOESI_CMP_directory.py Fri Mar 25 00:46:14 > 2011 -0400 > > +++ b/configs/ruby/MOESI_CMP_directory.py Fri Mar 25 10:13:50 > 2011 -0700 > > @@ -68,15 +68,19 @@ > > # Must create the individual controllers before the network to > ensure the > > # controller constructors are called before the network > constructor > > # > > + l2_bits = int(math.log(options.num_l2caches, 2)) > > + block_size_bits = int(math.log(options.cacheline_size, 2)) > > > > for i in xrange(options.num_cpus): > > # > > # First create the Ruby objects associated with this cpu > > # > > l1i_cache = L1Cache(size = options.l1i_size, > > - assoc = options.l1i_assoc) > > + assoc = options.l1i_assoc, > > + start_index_bit = block_size_bits) > > l1d_cache = L1Cache(size = options.l1d_size, > > - assoc = options.l1d_assoc) > > + assoc = options.l1d_assoc, > > + start_index_bit = block_size_bits) > > > > cpu_seq = RubySequencer(version = i, > > icache = l1i_cache, > > @@ -91,9 +95,7 @@ > > sequencer = cpu_seq, > > L1IcacheMemory = l1i_cache, > > L1DcacheMemory = l1d_cache, > > - l2_select_num_bits = \ > > - math.log(options.num_l2caches, > > - 2)) > > + l2_select_num_bits = l2_bits) > > > > exec("system.l1_cntrl%d = l1_cntrl" % i) > > # > > @@ -102,12 +104,15 @@ > > cpu_sequencers.append(cpu_seq) > > l1_cntrl_nodes.append(l1_cntrl) > > > > + l2_index_start = block_size_bits + l2_bits > > + > > for i in xrange(options.num_l2caches): > > # > > # First create the Ruby objects associated with this cpu > > # > > l2_cache = L2Cache(size = options.l2_size, > > - assoc = options.l2_assoc) > > + assoc = options.l2_assoc, > > + start_index_bit = l2_index_start) > > > > l2_cntrl = L2Cache_Controller(version = i, > > L2cacheMemory = l2_cache) > > diff -r bbab80b639cb -r d8587c913ccf configs/ruby/MOESI_CMP_token.py > > --- a/configs/ruby/MOESI_CMP_token.py Fri Mar 25 00:46:14 2011 - > 0400 > > +++ b/configs/ruby/MOESI_CMP_token.py Fri Mar 25 10:13:50 2011 - > 0700 > > @@ -82,15 +82,18 @@ > > # controller constructors are called before the network > constructor > > # > > l2_bits = int(math.log(options.num_l2caches, 2)) > > + block_size_bits = int(math.log(options.cacheline_size, 2)) > > > > for i in xrange(options.num_cpus): > > # > > # First create the Ruby objects associated with this cpu > > # > > l1i_cache = L1Cache(size = options.l1i_size, > > - assoc = options.l1i_assoc) > > + assoc = options.l1i_assoc, > > + start_index_bit = block_size_bits) > > l1d_cache = L1Cache(size = options.l1d_size, > > - assoc = options.l1d_assoc) > > + assoc = options.l1d_assoc, > > + start_index_bit = block_size_bits) > > > > cpu_seq = RubySequencer(version = i, > > icache = l1i_cache, > > @@ -123,13 +126,15 @@ > > cpu_sequencers.append(cpu_seq) > > l1_cntrl_nodes.append(l1_cntrl) > > > > + l2_index_start = block_size_bits + l2_bits > > + > > for i in xrange(options.num_l2caches): > > # > > # First create the Ruby objects associated with this cpu > > # > > l2_cache = L2Cache(size = options.l2_size, > > assoc = options.l2_assoc, > > - start_index_bit = l2_bits) > > + start_index_bit = l2_index_start) > > > > l2_cntrl = L2Cache_Controller(version = i, > > L2cacheMemory = l2_cache, > > @@ -158,9 +163,7 @@ > > size = \ > > > dir_size), > > memBuffer = mem_cntrl, > > - l2_select_num_bits = \ > > - > math.log(options.num_l2caches, > > - 2)) > > + l2_select_num_bits = > l2_bits) > > > > exec("system.dir_cntrl%d = dir_cntrl" % i) > > dir_cntrl_nodes.append(dir_cntrl) > > diff -r bbab80b639cb -r d8587c913ccf configs/ruby/MOESI_hammer.py > > --- a/configs/ruby/MOESI_hammer.py Fri Mar 25 00:46:14 2011 - > 0400 > > +++ b/configs/ruby/MOESI_hammer.py Fri Mar 25 10:13:50 2011 - > 0700 > > @@ -78,17 +78,21 @@ > > # Must create the individual controllers before the network to > ensure the > > # controller constructors are called before the network > constructor > > # > > + block_size_bits = int(math.log(options.cacheline_size, 2)) > > > > for i in xrange(options.num_cpus): > > # > > # First create the Ruby objects associated with this cpu > > # > > l1i_cache = L1Cache(size = options.l1i_size, > > - assoc = options.l1i_assoc) > > + assoc = options.l1i_assoc, > > + start_index_bit = block_size_bits) > > l1d_cache = L1Cache(size = options.l1d_size, > > - assoc = options.l1d_assoc) > > + assoc = options.l1d_assoc, > > + start_index_bit = block_size_bits) > > l2_cache = L2Cache(size = options.l2_size, > > - assoc = options.l2_assoc) > > + assoc = options.l2_assoc, > > + start_index_bit = block_size_bits) > > > > cpu_seq = RubySequencer(version = i, > > icache = l1i_cache, > > _______________________________________________ > > m5-dev mailing list > > m5-dev@m5sim.org > > http://m5sim.org/mailman/listinfo/m5-dev > > > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
