Everyone, this change alters the way that the O3 cpu switches registers from the atomic cpu. If you use checkpoint/switchover and m5 please test this (specifically the change to src/cpu/o3/thread_context_impl.hh)
Thanks, Ali On Mar 30, 2011, at 4:55 PM, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/620/ > ----------------------------------------------------------- > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works. > > This change fixes a small bug in the arm copyRegs() code where some registers > wouldn't be copied if the processor was in a mode other than MODE_USER. > Additionally, this change simplifies the way the O3 switchCpu code works by > utilizing TheISA::copyRegs() to copy the required context information > rather than the adhoc copying that goes on in the CPU model. The current code > makes assumptions about the visibility of int and float registers that aren't > true for all architectures in FS mode. > > > Diffs > ----- > > src/arch/arm/isa.cc d54b7775a6b0 > src/arch/arm/miscregs.hh d54b7775a6b0 > src/arch/arm/utility.cc d54b7775a6b0 > src/cpu/o3/thread_context_impl.hh d54b7775a6b0 > > Diff: http://reviews.m5sim.org/r/620/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
