Looks like Nilay is getting used to our style :) On Thu, Mar 31, 2011 at 2:19 PM, Nilay Vaish <ni...@cs.wisc.edu> wrote:
> This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/627/ > > src/mem/ruby/system/WireBuffer.hh<http://reviews.m5sim.org/r/627/diff/1/?file=11406#file11406line57> > (Diff > revision 1) > > class Consumer; > > 57 > > class Message; // I added this and removed Message.hh > > Remove the comment. > > > > src/mem/ruby/system/WireBuffer.hh<http://reviews.m5sim.org/r/627/diff/1/?file=11406#file11406line91> > (Diff > revision 1) > > class Consumer; > > 91 > > // int m_dummy; > > Remove this line as well. > > > > src/mem/ruby/system/WireBuffer.py<http://reviews.m5sim.org/r/627/diff/1/?file=11408#file11408line31> > (Diff > revision 1) > > 31 > > #from Controller import RubyController > > Do we need this commented piece of code? > > > - Nilay > > On March 31st, 2011, 12:21 p.m., Lisa Hsu wrote: > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > By Lisa Hsu. > > *Updated 2011-03-31 12:21:07* > Description > > Ruby: Add new object called WireBuffer to mimic a Wire. > This is a substitute for MessageBuffers between controllers where you don't > want messages to actually go through the Network, because requests/responses > can > always get reordered wrt to one another (even if you turn off Randomization > and turn on Ordered) > because you are, after all, going through a network with contention. For > systems where you model > multiple controllers that are very tightly coupled and do not actually go > through a network, > it is a pain to have to write a coherence protocol to account for mixed up > request/response orderings > despite the fact that it's completely unrealistic. This is *not* meant as a > substitute for real > MessageBuffers when messages do in fact go over a network. > > Diffs > > - src/mem/protocol/RubySlicc_Types.sm (d8587c913ccf) > - src/mem/ruby/SConscript (d8587c913ccf) > - src/mem/ruby/system/SConscript (d8587c913ccf) > - src/mem/ruby/system/WireBuffer.hh (PRE-CREATION) > - src/mem/ruby/system/WireBuffer.cc (PRE-CREATION) > - src/mem/ruby/system/WireBuffer.py (PRE-CREATION) > - src/mem/slicc/symbols/StateMachine.py (d8587c913ccf) > > View Diff <http://reviews.m5sim.org/r/627/diff/> > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
